Leuven, Belgium – May 25, 2011 – NVIDIA, a world-leader in visual computing technologies, signed a 3-year research collaboration agreement with imec on advanced CMOS scaling. By joining imec’s core CMOS program as INSITE member, NVIDIA will get early insight in the impact of future process and design technology options on its next-generation products.

NVIDIA joins the growing fabless community of imec’s core CMOS program. The collaboration focuses on the system design impact of advanced devices, interconnect, including 3D, and lithography implications for the sub-20nm node.

Imec INSITE makes … Read More → "Imec welcomes NVIDIA as fabless partner in its advanced CMOS scaling program"

Leuven, Belgium – May 26, 2011 – Imec and its partners in the GaN industrial affiliation program (IIAP) have produced device-quality wafers with GaN/AlGaN layers on 200mm silicon wafers. With these wafers, functional GaN MISHEMTs were processed using standard CMOS tools. The used processes are compatible with the strict contamination rules in a standard CMOS processing line (e.g. no use of gold). These first GaN devices on 200mm wafers are an important milestone on the path to cost-effective production of power devices in high-productivity 200mm fabs.

GaN is a promising material for next-generation power devices with … Read More → "Imec processes first power devices on 200mm CMOS-compatible GaN-on-Si"

SAN DIEGO, CA–(Marketwire – May 25, 2011) –

Who/What

Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company, in the post-layout verification market focused on solutions for nanometer design applications, is attending the 48^th Design Automation Conference (DAC) in San Diego and will show its newest product  … Read More → "Silicon Frontline Addresses EDA Industry Bottleneck, Promotes Guaranteed Accurate 3D Post-Layout Extraction at Design Automation Conference"