LOS GATOS, Calif., June 2, 2011 – IC Manage, Inc. today announced that the IC Manage Global Design Platform (GDP) has been extended to include IP Central, an open platform for maximizing IP reuse. Design and verification teams can use IP Central to rapidly publish and integrate IP into existing flows, and to trace bug dependencies. Internal and third party IP can be imported or linked with IP Central from multiple commercial and open source design management systems, as well as internal revision control systems.& … Read More → "IC Manage Announces IP Central to Maximize IP Reuse"

MOUNTAIN VIEW, Calif., June 2, 2011 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced its close cooperation with STMicroelectronics (ST) in the successful tapeout of ST’s first 20-nanometer (nm) technology demonstrator test chip. This tapeout represents a critical milestone in the R&D collaboration between the two companies to develop a comprehensive design enablement solution for system-on-chip (SoC) integrated circuits (ICs) using ST’s next-generation 20-nm process technology, co-developed with its ISDA (International Semiconductor Development Alliance) partners in Fishkill, NY.

R&D teams from … Read More → "Synopsys Collaborates With STMicroelectronics to Help Achieve Critical Milestone in 20-nm Design"

FREIBURG, Germany – June 2, 2011 – Design and verification engineers who work on complex analog/ mixed-signal (AMS) designs or who need to customize and integrate analog or digital IP building blocks into their system-on-chip (SoC) or integrated circuit (IC) designs will be able to assess a new analysis and debugging tool at DAC 2011. Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, etc.) as well as with different design languages and … Read More → "Concept Engineering Introduces Integrated Debugging Tool for Mixed-signal Design at DAC 2011"

SANTA CLARA, CALIF. –– June 2, 2011 — Oasys Design Systems today announced that its Chip Synthesis™ platform, in use in production environments, now includes design for test (DFT) capabilities, further extending the fast speed and high capacity of Oasys’ RealTime Designer™ software. 

This follows an earlier announcement that the Chip Synthesis platform supports chip-level power analysis and optimization, and has the ability to synthesize a design from the register transfer level (RTL) with UPF … Read More → "Oasys Design Systems adds DFT Capabilities to Chip Synthesis"

WILSONVILLE, Ore., May 31, 2011 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Catapult^® C high-level synthesis tool now supports the synthesis of transaction level models (TLM). TLM synthesis provides the foundation for an executable methodology allowing interplay between Catapult C Synthesis and the Vista™ platform, resulting in a complete TLM 2.0-based solution for virtual prototyping and hardware implementation and enabling the creation of synthesis-ready virtual platforms.

Expanding its full-chip synthesis technology, the Catapult … Read More → "Mentor Graphics Forges TLM Synthesis Link Between Hardware Implementation and Virtual Prototyping"