SANTA CLARA, Calif., and Nashua, NH, Nov. 9, 2009 — Agilent Technologies Inc. and Nexus Technology Inc. today made available DDR3-1867 DIMM and DDR3-1600 SODIMM slot interposer test solutions. These test solutions are the ideal tools for designers performing DDR3 DIMM or SODIMM validation, failure analysis, and bus functional-parametric validation in servers, supercomputing, desktops, laptops and computing applications.

The test solutions are comprised of the Agilent 16962A logic analyzer module and either a Nexus NT-DDR3DIHS or Nexus NT-DDR3SOIHS slot interposer for next-generation, double-data rate (DDR3) SDRAM buses.

The new interposers are designed for … Read More → "Agilent Technologies, Nexus Technology Deliver DDR3 Memory Bus Debug Solutions"

HILLSBORO, OR — NOVEMBER 10, 2009 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced it will collaborate with Beyond Semiconductor in the development of compiler tools for Lattice’s soft processors. The collaboration will include updates and performance improvements for Lattice’s embedded processor IP compilers and development tools.

Lattice’s LatticeMico8™ embedded microcontroller and LatticeMico32™ embedded microprocessor are optimized for implementation in Lattice FPGAs and PLDs. These embedded processors are provided free of charge through an innovative open source intellectual property (IP) core license that provides customers access to the HDL for … Read More → "Lattice And Beyond Semiconductor To Collaborate In Processor Compiler Tools Development"

— Version 8.0 Software Helps Build High Speed, Robust, Double Data Rate Interfaces —

HILLSBORO, OR — NOVEMBER 10, 2009 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 8.0 of its ispLEVER® FPGA design tool suite, which includes many enhancements for the design of high speed double data rate (DDR) interfaces for the LatticeECP3™ FPGA family. These enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.
“Although our ECP3 FPGA family probably is best known for its low … Read More → "New Lattice FPGA Design Tool Suite Includes Advanced Support For High Performance DDR Interfaces"

– Extessy adds system requirements, co-simulation, integration and test tools to Artisan’s product portfolio

– Further extends Artisan’s professional services capability and expands German operations

Washington DC, USA and Cheltenham, UK – 10th November 2009. Artisan® Software Tools, the world’s largest independent supplier of industrial-grade, collaborative modeling tools for complex, mission and safety-critical embedded systems and software, has acquired Extessy, a leading supplier of development tools and services for system requirements, co-simulation, integration and test, based in Wolfsburg, Germany. Artisan’s acquisition of Extessy closely follows its acquisition last … Read More → "Artisan continues industry consolidation with Extessy merger"

– PAC-Designer 5.2 Tools Support New Power Manager II Devices; Ideal for 
Integrated Hot Swap Control, Supervision and Sequencing; Adds HDL Verification to Flow –

HILLSBORO, OR — NOVEMBER 9, 2009 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 5.2 of its PAC-Designer® mixed signal design tool suite with new device support and productivity features. The PAC-Designer 5.2 software now supports two new higher performance Power Manager II products: the ispPAC®-POWR1014-2 and ispPAC-POWR1014A-2 devices. The POWR1014/A-2 devices are ideal for integrating Hot Swap control, voltage rail supervision and power supply sequencing ICs. … Read More → "Lattice Updates Software Design Tools For Hot Swap Control and Power Management"

SANTA CLARA, Calif., Nov. 2, 2009 — Agilent Technologies Inc. (NYSE: A) today introduced a compact network analyzer, the Agilent E5061B, that analyzes a frequency range as low as 5 Hz up to the RF (radio frequency) range of 3 GHz. This network analyzer’s broad range and versatility eliminates the need for additional low-frequency-dedicated instruments.

Applications for the Agilent E5061B, part of the ENA series of network analyzers, include general RF-network measurements, such as filters or amplifier tests, and LF (low frequency) measurements necessary for loop-gain evaluation of DC-DC converters. The E5061B’s frequency coverage is suitable … Read More → "Agilent Technologies Introduces Versatile, Compact Network Analyzer with Wide Frequency Range"

WHO: The Open SystemC Initiative (OSCI), an independent, non-profit organization dedicated to supporting and advancing SystemC™ as an industry-standard language for electronic system-level (ESL) design, today announced the release of the draft 1.3 standard of the SystemC Synthesis Subset.

WHAT: The Synthesis Subset Draft 1.3 standard is intended for use by logic designers, electronic engineers and design automation tool developers. It describes a standard syntax and semantics for SystemC synthesis. The standard includes hardware constructs at the behavioral and register-transfer levels, and is based on the ANSI C++ standard and the IEEE 1666™-2005 Standard for SystemC. … Read More → "OSCI Introduces SystemC Synthesis Subset Draft Standard – Opens for Public Review – Review Period Runs Through January 31, 2010"

Fareham, UK: EDA Solutions announces that X-FAB has released two 0.18µm process design kits (PDK) for Tanner Tools Pro on X-TIC, X-FAB’s online technical database. Tanner Tools Pro is the software suite for the design, layout and verification of analog, mixed-signal (A/MS), RF and MEMS ICs from Tanner EDA, the world leader in PC-based A/MS and MEMS circuit design software. The release of this new kit extends X-FAB’s PDK support for Tanner tools, adding X-FAB’s 0.18µm processes to the range of technologies currently supported (0.35, 0.6, 0.8 and 1.0µm). The new PDK … Read More → "EDA Solutions announces Tanner EDA process design kit support for X-FAB’s 0.18µm technologies"

Sunnyvale, CA and Tokyo, Japan. — Nov 3rd, 2009 — Mirabilis Design Inc., today announced that VisualSim was used by a joint venture project involving TOPS Systems of Japan, to model, simulate and analyze the performance of a Real-Time Ray Tracing system with distributed software and a heterogeneous Multi-Core processor. The architecture development and software partitioning were conducted by developing performance and power models using the standard libraries in the VisualSim graphical environment. This model was used to optimize the processor architecture, application algorithms and data distribution to achieve 800 Tera floating point operations per second (TeraFLOPS).

“ … Read More → "VisualSim enabled engineers to architect the software and processor to achieve 800 Teraflops for a Real-Time Ray Tracing system."

MOUNTAIN VIEW, Calif., Nov. 5, 2009 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Realtek Semiconductor Corp, a leading provider of advanced IC products for communications network, computer peripheral and multimedia applications, has signed an expanded business agreement establishing Synopsys as its primary EDA partner. Under the new multi-year agreement, Realtek has extended its use of Synopsys’ Galaxy(tm) Implementation, Discovery(tm) Verification and Confirma(tm) Rapid Prototyping Platforms, as well as Synopsys’ DesignWare(r) IP and consulting services.

“By selecting Synopsys as … Read More → "Synopsys chosen by Realtek as its primary EDA partner"