SAN JOSE, CA–(Marketwire – October 05, 2011) – “Creating an advanced mixed-signal SoC presents significant challenges,” said Dr. Jens Kosch, chief technology officer at X-FAB. “Our customers welcome any opportunity to streamline the development process, so we were pleased to qualify and endorse the Cadence Physical Verification System for our process technologies at X-FAB.”Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that X-FAB, a leading foundry group for analog/mixed-signal semiconductor applications, has qualified the Cadence® Physical … Read More → "X-FAB Qualifies Cadence Physical Verification System for All Process Nodes"

SAN JOSE, CA–(Marketwire – October 05, 2011) – “More and more leading companies are recognizing the time-to-market advantages they can attain by using the Cadence Virtuoso Accelerated Parallel Simulator,” said John Pierce, product marketing director, custom simulation, Silicon Realization at Cadence. “Integrating tightly and seamlessly with the Virtuoso Analog Design Environment, the simulator beats baseline SPICE simulation performance and enables companies like Fuji Electric to conduct more thorough, comprehensive verification, reducing risk and improving quality.”Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic … Read More → "Fuji Electric Cuts Development Time 25 Percent With Cadence Virtuoso Accelerated Parallel Simulator"