MOUNTAIN VIEW, Calif., Aug. 23 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced it will be hosting its first Synposium, a virtual trade show event where attendees around the world can learn about Synopsys’ EDA software, IP, prototyping and services from the convenience of their desks. During the first three days of the event, Synopsys staff will be available to chat online in this interactive online format. Synposium attendees can view the materials on-demand through December 3, 2010.

What: Synopsys Synposium, a Virtual Event
… Read More → "Synopsys to Host First Synposium Virtual Event"

San Jose, California – August 16, 2010 – InPA Systems, Inc. has been formed to develop and market FPGA-based rapid prototyping technology that allows users to … Read More → "InPA Systems Inc. Targets Active Debug™ for Rapid Prototyping"

NEW YORK –– August 17, 2010 –– Luca Daniel, Emanuel E. Landsman associate professor of Electrical Engineering at Massachusetts Institute of Technology, has been chosen as this year’s recipient of the Early Career Award from the IEEE Council on Electronic Design Automation (CEDA). 

Professor Daniel will be recognized for his contribution to electromagnetic field analysis, parasitic variation-aware extraction and automated parameterized linear and non-linear stable model reduction during ICCAD’ … Read More → "IEEE Council on EDA to Honor MIT’s Luca Daniel with Early Career Award"

HILLSBORO, OR — AUGUST 16, 2010 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of Version 1.4 of its ispLEVER® Classic design tool suite.  The ispLEVER Classic design software has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH® 4000ZE CPLD fitter with improved power optimization. 

Synplify Pro HDL Analyst provides designers a way to rapidly visualize high-level register transfer level (RTL) Verilog or VHDL.  Designers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is … Read More → "Lattice Announces Improved Synthesis And Power Optimization in CPLD Tools"

MOUNTAIN VIEW, Calif. – August 12, 2010 — Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the launch of the DesignWare® USB Software Alliance Program with leading USB software providers emsys, Jungo, MCCI and MicroDigital as inaugural members. This alliance program establishes an ecosystem of qualified USB software providers for drivers, firmware and stacks which have proven interoperability with Synopsys’ DesignWare USB 2.0 and SuperSpeed USB 3.0 IP. Synopsys and its DesignWare USB Software Alliance Program members can help designers to quickly incorporate USB connectivity into their system-on-chips (SoCs) with … Read More → "Synopsys launches DesignWare USB software alliance program"

CONCORD, CA – AUGUST 11 , 2010 — D-Tools Inc., the worldwide leader in system integration software today announced that detailed information on of the entire family of Atlona products has been recently updated in D-Tools product database, better enabling D-Tools System Integrator™ users to specify Atlona products. 

Atlona Technologies is a dynamic solutions based manufacturer poised on the bleeding edge of Audio Video technology. Their product line has grown to cover almost every conceivable solution in the Audio Video industry with new innovative products in development continuously. Atlona has been consistently first to market without sacrificing … Read More → "Atlona Technologies Product Line Now Updated In D-Tools System Integrator (SI) 5.5 Software"

MOUNTAIN VIEW, Calif. – August 11, 2010 – Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of the Time Division Duplex (TDD) mode in its Long-term Evolution (LTE) Model Library for physical layer system simulation. The addition of the TDD mode to the proven LTE Model Library enables developers of semiconductors for LTE network equipment and devices to quickly and reliably extend their designs to support this important version of the 3rd Generation Partnership Project (3GPP) LTE standard.

The 3GPP LTE standard is the latest standard … Read More → "Synopsys adds TDD support to LTE Model Library"

MOUNTAIN VIEW, Calif. — August 9, 2010 — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that TSMC has successfully taped out a complex 28 nanometer (nm) Product Qualification Vehicle (PQV) test chip using Synopsys’ Galaxy(tm) Implementation Platform. Key features used to design the PQV test chip include 28nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities. Synopsys tools exercised by TSMC in the RTL-to-GDSII implementation and signoff flow for this test … Read More → "Synopsys Galaxy Implementation Platform used by TSMC for 28nm process"

Bristol, UK and Sunnyvale, Calif. – August 3^rd, 2010–XMOS® today announces that its customers, Meridian, Intelligent Media Technologies and High Resolution Technologies, have lowered development costs, shortened time to market and increased design flexibility to produce more differentiated products by using XMOS event-driven processors™. XMOS programmable chips bring together the capabilities of processors, DSPs and FPGAs, to help design economical electronic products at exceptional speed. 

“Embedded design and development … Read More → "XMOS Customers Build Better Products, Faster"

MOUNTAIN VIEW, Calif.  August  4, 2010 — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and GLOBALFOUNDRIES, a leading provider of advanced semiconductor technology and manufacturing services, today announced an agreement to develop the Synopsys DesignWare®SuperSpeed USB (3.0), USB 2.0, HDMI 1.4 Tx and Rx, DDR3/2, PCI Express® 2.0 and 1.1, SATA 1.5/3 Gbps and 6 Gbps, and XAUI  PHY IP for GLOBALFOUNDRIES’ 28 nanometer (nm) “Gate First” High-k Metal Gate (HKMG) process technologies. The collaboration will enable mutual customers to differentiate their 28nm designs with a high quality IP … Read More → "Collaboration enables faster time-to-volume for advanced high performance SoC designs"