News – Page 2014 – EEJournal

New Reference Designs Enhance Embedded Function Block Of Lattice MachXO2 PLD Family

June 4, 2012

HILLSBORO, OR – JUNE 4, 2012 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of four new reference designs for the low cost, low power MachXO2™ family of programmable logic devices (PLDs). The new reference designs simplify and enhance the usability of the built-in I2C, SPI and User Flash Memory functions in the MachXO2 device’s unique Embedded Function Block (EFB). Five new demonstration designs and three updated application notes focused on the embedded, Flash memory-based EFB are also now available.

Since the MachXO2 family’s … Read More → "New Reference Designs Enhance Embedded Function Block Of Lattice MachXO2 PLD Family"

Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20nm Phase I Certification

June 4, 2012

SAN FRANCISCO, CA–(Marketwire – June 04, 2012) – DAC Booth # 1930 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff.

TSMC certified the tools for 20-nanometer design rule manuals (DRMs) and SPICE models. Early adopters are using the flows and tools while close collaboration continues between TSMC, Cadence and designers.

The Cadence Read More → "Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20nm Phase I Certification"

Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform

June 4, 2012

DESIGN AUTOMATION CONFERENCE, San Francisco, CA, June 4, 2012 –A new electronic design automation (EDA) company and a groundbreaking new product were launched at DAC 2012 today. Ausdia delivers a comprehensive timing constraints development, verification and management solution that complements all implementation and timing signoff flows. Ausdia’s Timevision, an innovative timing constraint development solution, integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run. Timevision helps designers create good SDC/TCL constraints and is a verification platform for existing timing constraints. The company’s … Read More → "Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform"

Cadence Collaborates on 3D-IC Design Infrastructure With TSMC

June 4, 2012

SAN FRANCISCO, CA–(Marketwire – June 04, 2012) – DAC Booth # 1930 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its collaboration with TSMC on 3D-IC design infrastructure development.

3D-ICs require co-design, analysis and verification of heterogeneous chips and silicon carriers. Coming from multiple disciplines and product areas, TSMC and Cadence teams worked together to create and integrate features to support this new type of design, culminating in the test-chip tapeout of TSMC’s first heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) vehicle.

Novel Current-Sharing, Diode-OR Controller Eases Design of Reliable Power Systems

June 4, 2012

MILPITAS, CA – June 4, 2012 – Linear Technology Corporation introduces the LTC4370, a first-of-its-kind current-sharing controller with reverse current blocking. The LTC4370 frees the designer from the limitations and complications of existing current-sharing methods to obtain a simpler, quicker, and space-saving solution for sharing between two supplies. Its supply-agnostic feature lends the design more flexibility and a longer lifetime. By incorporating diode behavior, the controller prevents one supply … Read More → "Novel Current-Sharing, Diode-OR Controller Eases Design of Reliable Power Systems"

MunEDA presents the integration of its WiCkeD design tool with Agilent Technologies’ GoldenGate simulator at DAC

June 4, 2012

San Francisco – USA – June 4, 2012 – MunEDA today announced that it and Agilent Technologies Inc. have integrated MunEDA’s software productWiCkeD^TM for circuit porting, analysis and optimization with Agilent’s GoldenGate RFIC simulation and analysis software to enhance and speed up the analysis, modelling and optimization of RF circuits.

The integrated solution is now available for customer use. It will be presented by MunEDA and Agilent at the 2012 Design Automation Conference (DAC) in San Francisco, June 4 … Read More → "MunEDA presents the integration of its WiCkeD design tool with Agilent Technologies’ GoldenGate simulator at DAC"

Target Compiler Technologies Releases New Multicore Debugger for its MP Designer Product Line

June 4, 2012

49th Design Automation Conference – San Francisco, California, June 4, 2012. Target Compiler Technologies, the leader in ASIP design tools, today announced the commercial release of a new graphical debugger tool for multicore system-on-chip architectures. The new multicore debugger, named ChessMP™, seamlessly integrates with Target’s instruction-set simulation technology for processor cores, thus enabling cycle and instruction-accurate simulation of multicore architectures. Additionally, ChessMP easily connects to FPGA and ASIC implementations of the multicore system through a JTAG-based communication API, thus enabling multicore on-chip debugging.

Today’s release of the ChessMP multicore debugger marks the first phase in the commercial release … Read More → "Target Compiler Technologies Releases New Multicore Debugger for its MP Designer Product Line"

Synopsys Launches Industry’s First Integrated Hybrid Prototyping Solution

June 4, 2012

MOUNTAIN VIEW, Calif., June 4, 2012 –

Highlights:

Get the best of both worlds with a hybrid prototype that seamlessly links virtual and FPGA-based prototypes
Start multi-core SoCprototyping earlier and achieve high-performance execution of system-level models with directly connected real-world hardware interfaces
Partition SoC design blocks between virtual and FPGA-based prototype environments to maximizeoverall prototype performance
Accelerate system bring-upby using virtual prototyping for new design blocks and FPGA-based prototyping for existing logic
Improve debug visibility and control of software under development through the Virtualizer-based environment
Easily … Read More → "Synopsys Launches Industry’s First Integrated Hybrid Prototyping Solution"

Invensense® Expands Into Industrial Applications With The World’s First Single-Chip, Integrated High-Performance 3-AXIS Industrial Gyroscope

June 4, 2012

SUNNYVALE, Calif., June 4, 2012 – – InvenSense, Inc. (NYSE: INVN), the leading provider of MotionTracking^™devices, today announced its entry into the industrial market with the introduction of its MPU-3300, the … Read More → "Invensense® Expands Into Industrial Applications With The World’s First Single-Chip, Integrated High-Performance 3-AXIS Industrial Gyroscope"

TI makes LED lighting design easy and fast

June 1, 2012

DALLAS (May 30, 2012) – Texas Instruments Incorporated (TI) (NASDAQ: TXN) today introduced two fully integrated LED driver micro-modules that eliminate the external components and complex layout placement challenges typical of LED driver designs. The 450-mA TPS92550 and TPS92551 DC/DC LED driver modules are the industry’s first to incorporate all the required power and passive circuitry into a single IC package to deliver up to 23W of power to the LED. Watch a video … Read More → "TI makes LED lighting design easy and fast"