SAN JOSE, Calif., October 27, 2021—Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the immediate availability of Cadence® IP supporting the PCI Express® (PCIe®) 6.0 specification on the TSMC N5 process. The Cadence IP for PCIe 6.0 consists of a high-performance DSP-based PHY and a feature-rich companion controller to deliver the optimized performance and throughput for next-generation applications in hyperscale computing and 5G communications, including networking, emerging memory and storage. Early adopters of Cadence IP for PCIe 6.0 can access design kits now.
The 5nm PCIe 6.0 PHY test chip silicon from Cadence demonstrated excellent electrical performance across all PCIe rates. The … Read More → "Cadence Demonstrates IP Test Silicon for PCI Express 6.0 Specification on TSMC N5 Process"