Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs
Henderson, NV – February 6, 2023 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated its popular linting tool ALINT-PRO to enhance the support of Microchip Technology’s Libero® SoC Design Suite. The new release supports automatic conversion of Libero projects into ALINT-PRO’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.
Static linting helps detect a wide variety of design issues, including poor coding styles, improper clock and reset management, simulation vs. synthesis mismatches, incorrectly implemented finite state machines ( … Read More → "Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs"
