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NANIUM Extends Wafer-Level Packaging (WLP) Offer by Including Fan-In WLP Volume Production On 300mm Wafers

PORTO, Portugal – Nov. 7, 2012 – NANIUM, a leading provider of semiconductor packaging, test and engineering services, today announced that it has extended its offering to include fan-in WLP volume production on 300mm wafers.

NANIUM earlier this year licensed Flip Chip International’s (FCI) Spheron® Plated Cu Redistribution technology to provide solutions for 300mm wafer-level chip scale packaging (WLCSP) using fan-in WLP processes. After completing line setup and qualification for that technology, the company added the capability to manufacture fan-in WLP products, which extends its service portfolio using the latest technology on 300mm wafers.

“The conventional fan-in variant … Read More → "NANIUM Extends Wafer-Level Packaging (WLP) Offer by Including Fan-In WLP Volume Production On 300mm Wafers"

Mentor Graphics New Tessent IJTAG Product Automates IP Test and Debug Integration in Large SoC Designs

WILSONVILLE, Ore., November 6, 2012-Mentor Graphics Corporation (NASDAQ:MENT) today announced its new TessentR IJTAG solution, which allows designers to easily reuse test, monitoring and debugging logic embedded in existing IP blocks. Supporting the IEEE P1687 (IJTAG) standard, the solution automatically retargets test and debug commands and generates an integrated hierarchical control and data network with a single top-level interface for an entire SoC. The solution, which supports any embedded instrumentation compliant to the P1687 standard, can be used where pin count is limited or </ … Read More → "Mentor Graphics New Tessent IJTAG Product Automates IP Test and Debug Integration in Large SoC Designs"

Aldec Boosts VHDL Simulation Performance

Henderson, NV – November 5, 2012 – Aldec, Inc. announced the release of its mixed language advanced verification platform,Riviera-PRO™ 2012.10.  The release delivers numerous stability and performance improvements, support for the latest versions of industry-standard SystemVerilog verification libraries, new language constructs, new debugging tools, and improved interfaces to other industry leading EDA tools. 

Riviera-PRO delivers a 20% VHDL simulation performance gain over previous releases. “We keep developing and delivering not only new productivity features, but also innovative core engine optimizations to boost simulation performance in VHDL and SystemVerilog to support the … Read More → "Aldec Boosts VHDL Simulation Performance"

Agilent Technologies Introduces Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links

SANTA CLARA, Calif., Nov. 5, 2012 – Agilent Technologies Inc. (NYSE:A) today introduced a redriver modeling solution designed to quickly and accurately solve the challenge posed by signal distortion in multigigabit-per-second systems.

The redriver modeling solution, available in the Advanced Design System 2012 Transient Convolution Element and SystemVue 2012 AMI Modeling Kit, is used to design electrical redrivers into high-speed chip-to-chip digital links.

Before the multigigabit era, chip-to-chip digital signals could propagate across an entire … Read More → "Agilent Technologies Introduces Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links"

3.5 Inch Embedded SBC with Intel Atom Processor “Cedar Trial” N2800

Acrosser Technology Co. Ltd, global professional industrial and embedded computer provider, announces the new3.5” SBCAMB-N280S1, which carries the Intel dual- core 1.8 GHz Atom Processor N2800. Acrosser takes advantage of Atom Cedar Trail N2000 series processor in design, such as low power consumption and small footprint as former Atom series. With Read More → "3.5 Inch Embedded SBC with Intel Atom Processor “Cedar Trial” N2800"

Cadence Encounter Technologies Enable Open-Silicon to Reach 2.2 GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor

BANGALORE, INDIA–(Marketwire – November 06, 2012) – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Open-Silicon, Inc., a leading semiconductor design and manufacturing company, has leveraged the latest innovations from the Cadence® Encounter® RTL-to-signoff flow to achieve 2.2 GHz performance on a 28-nanometer hardening of an ARM® dual-core Cortex™-A9 processor.

Open-Silicon used the latest Read More → "Cadence Encounter Technologies Enable Open-Silicon to Reach 2.2 GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor"

Tokyo Electron Device Announces Release of TB-7V-2000T-LSI ASIC Development Test Platform with Virtex-7 FPGA

Yokohama, Japan, November 6, 2012 – Tokyo Electron Device Limited (TED) has today announced the  release of the TB-7V-2000T-LSI ASIC development test platform featuring a Xilinx Virtex®-7 FPGA.

Released under TED’s inrevium* brand, the TB-7V-2000T-LSI is intended for development of large SoCs  and incorporates a Virtex-7 2000T FPGA, the world’s largest FPGA with performance features that include high-speed internal logic and high-bandwidth interfaces. This makes it possible to perform emulation and prototyping of large SoCs using a single FPGA instead of the multiple chips required in the past. Whereas operating speed can be … Read More → "Tokyo Electron Device Announces Release of TB-7V-2000T-LSI ASIC Development Test Platform with Virtex-7 FPGA"

Synopsys Introduces Memory Test and Repair Solution for Designs at 20 Nanometers and Below

MOUNTAIN VIEW, Calif., Nov. 6, 2012 /PRNewswire/ —

Highlights:

  • Optimized memory test and repair algorithms efficiently address new memory defects,  including process variation faults and resistive faults, at 20 nanometers (nm) and below
  • New hierarchical architecture delivers up to 30 percent reduction in memory test and repair area
  • Hierarchical implementation accelerates design cycles by allowing incremental generation,  integration and verification of test and repair IP at various design hierarchy levels 
  • Support for test interfaces of high-performance processor cores enables designers to maximize productivity and system-on-chip (SoC) performance  
< … Read More → "Synopsys Introduces Memory Test and Repair Solution for Designs at 20 Nanometers and Below"

Nallatech Qualifies FPGA Accelerators for IBM PureFlex™ System

CAMARILLO, Calif., – November 5, 2012 – Nallatech, a leading supplier of high-performance FPGA solutions, today announced it has qualified two FPGA-based PCI Express accelerator cards for the new IBM PureFlexTM System. 

IBM PureFlex is an infrastructure system that provides an integrated computing platform combining servers, storage, networking, visualization and management into a single structure. PureFlex allows customers to increase IT efficiency, minimize risk and lower costs. 

Nallatech is IBM’s only Industry Solutions Reseller (ISR) partner specializing in FPGA solutions. Nallatech has extensive experience integrating and testing FPGA accelerator cards for IBM xSeries, BladeCenter and … Read More → "Nallatech Qualifies FPGA Accelerators for IBM PureFlex™ System"

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