Portland, Oregon, April 3, 2013 – FishTail Design Automation, Inc., the golden timing constraints company, today announced that Japan’s Semiconductor Technology Academic Research Center (STARC) has completed a study of FishTail’s solution for merging multi-mode design constraints. This study has demonstrated that FishTail’s products drastically reduce STA runtime without any compromise on timing accuracy.

STARC engineers conducted a detailed study of FishTail’s mode-merging solution on a 4 million cell instance SoC with 700K flops. The design had 18 design modes, each with 10 timing corners, resulting in a total of 180 STA verification scenarios. FishTail’s Focus product was used … Read More → "STARC Endorses FishTail for Automated Merging of Multi-Mode Design Constraints for Timing Signoff"

NAPA, Calif., April 3, 2013– Accellera Systems Initiative (Accellera), an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards for design and verification, today announces the formation of a new Multi-language Working Group (MLWG). The mission of the MLWG is to create a standard and functional reference for interoperability of multi-language verification environments and components.  Accellera is calling for participation in the newly formed group. Accellera members and the industry at large are invited to join the … Read More → "Accellera Systems Initiative Launches Working Group to Standardize Interoperability of Multiple Language Verification Environments and Components"

Ottawa, Canada – (April 1, 2013) – Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) one-time programmable (OTP) memory IP cores, announced today that the Company’s 1T-OTP macros for TSMC’s 180nm BCD 1.8/5V/HV and G 1.8/5V processes have met all of TSMC’s IP9000 Assessment program requirements. Sidense OTP macros are fully qualified for -40ºC to 150°C read and field-programmable operations to support applications such as automotive electronics that require reliable operation and long-life data retention in high-temperature environments.

Sidense has already licensed its Automotive Grade 1T-OTP macros to many top fabless semiconductor … Read More → "Sidense 1T-OTP NVM Qualified for 150 Degrees C Automotive High-Reliability Requirements on TSMC’s BCD Process"

SAN JOSE, CALIF. –– April 2, 2013 –– ProPlus Design Solutions, Inc. (www.proplussolutions.com), the global leader for SPICE modeling solutions and the leading technology provider for Design-for-Yield (DFY) applications, today launched NanoSpice™, the next-generation high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation.

In announcing NanoSpice, ProPlus unveiled an innovative licensing model with simplified and practical control for parallelization, making it a cost-effective and … Read More → "ProPlus Design Solutions Unveils Next-Generation Pure SPICE Simulator for Giga-Scale Simulations"