Delft University of Technology and imec Introduce 3D-COSTAR to Optimize Test Flows of 3D Stacked Integrated Circuits
Delft, the Netherlands and Leuven, Belgium – October 8, 2013 – Delft University of Technology (TU Delft) and nanoelectronics research center imec, today presented 3D-COSTAR, a new test flow cost modeling tool for 2.5/3D stacked integrated circuits (ICs). 3D-COSTAR aims to optimize the test flow of 3D stacked ICs (SICs), taking into account the yields and costs of design, manufacturing, packaging, test, and logistics.
Due to its many high-precision steps, semiconductor manufacturing is defect-prone. Consequently, every IC needs to undergo electrical tests to weed out defective parts and guarantee outgoing product quality to the customer. For TSV-based 2.5D- and 3D-SICs that … Read More → "Delft University of Technology and imec Introduce 3D-COSTAR to Optimize Test Flows of 3D Stacked Integrated Circuits"

