Cadence Digital and Custom/Analog Tools Achieve TSMC V1.0 DRM Certification for 16nm FinFET Process
SAN JOSE, Calif., April 15, 2014—Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its digital, custom and signoff tools have received V1.0 Design Rule Manual (DRM) and SPICE certification for TSMC’s 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence® tools. Cadence’s digital, custom/analog and signoff tools have been co-optimized with TSMC’s 16nm FinFET process to enable higher performance, lower power consumption and smaller area for advanced designs.
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