SAN JOSE, CALIF., and NOIDA, INDIA –– May 31, 2013 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software to enable design at a higher level of abstraction, and CircuitSutra(www.circuitsutra.com) announced today they will partner to provide design services throughout India … Read More → "Forte Design Systems, CircuitSutra Partner on Design Services, IP Co-Development"

Milpitas, Calif. — May 30, 2013 — At next week’s 50th Design Automation Conference (DAC) in Austin, Texas,GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes. The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches.

Multi-vendor support is available, with full implementation flows from Read More → "GLOBALFOUNDRIES Introduces Certified Design Flows for Multi-Die Integration Using 2.5D IC technology"

WILSONVILLE, Ore., May 30, 2013—Mentor Graphics Corp. (NASDAQ: MENT) today announced it has collaborated with GLOBALFOUNDRIES to deliver 20nm design kits for the Olympus-SoC™ netlist-to-GDS platform. The design kit enables mutual customers to achieve the best performance, power and area with faster design closure times.

“Double patterning and timing closure at advanced nodes require a comprehensive suite of design tools and methodologies,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “Mentor solutions, including Olympus-SoC, help ensure that designs using our 20nm technologies perform and yield well by efficiently utilizing our DRC+ technology to … Read More → "Mentor Graphics and GLOBALFOUNDRIES Deliver 20nm Design Kits for Advanced Design Enablement"

SAN JOSE, CA–(Marketwired – May 30, 2013) –

Cadence Design Systems, Inc. (NASDAQ: CDNS)

HIGHLIGHTSCadence Design Systems, Inc. (NASDAQ: CDNS)

• PMC is producing working silicon on 65- and 40-nanometer designs, and is currently deploying the product for its 28-nanometer designs.
• Technology chosen for turnaround time and ready foundry support
• Physical Verification System signoff decks certified by major foundries

Cadence Design … Read More → "PMC Adopts Cadence Physical Verification System as Signoff Technology for Large Complex SoC"

May 30, 2013, MOUNTAIN VIEW, Calif. — Jasper Design Automation, Inc., the leading provider of verification solutions based on state-of-the-art formal technology, and Duolog Technologies, the leading provider of SoC integration products and solutions, have announced a partnership to leverage the tools and methodologies of both companies. The companies’ integrated solutions will address the complex, time-consuming and error-prone tasks associated with SoC integration and verification. The integrated flows by Duolog and Jasper will enable IP/SoC development teams to deliver qualified, integration-ready IP and SoC … Read More → "Jasper and Duolog Partner to Combine SoC Integration with Formal Verification"