News – Page 1545 – EEJournal

Tailored Gyroscopes from STMicroelectronics Target Shake-Free Images on Mobiles and Cameras

September 10, 2013

Geneva, September 10, 2013 – STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the spectrum of electronics applications, the world’s top MEMS manufacturer, and the leading supplier of MEMS sensors for consumer and portable applications^[1], has introduced a new family of gyroscopes specifically optimized for optical image stabilization in smartphones and digital still cameras.

Optical Image Stabilization has become an essential feature in today’s smartphones and digital still cameras. By moving the lens in real time to compensate … Read More → "Tailored Gyroscopes from STMicroelectronics Target Shake-Free Images on Mobiles and Cameras"

Altera Demonstrates Broadcast Solutions at IBC 2013

September 10, 2013

Amsterdam, IBC 2013 Conference — Sept. 10, 2013—Altera Corporation (NASDAQ: ALTR) is sharing its latest innovations in programmable logic devices for diverse broadcast end-market applications at IBC 2013 in Amsterdam from September 13 to 17.

Altera is demonstrating how its field programmable gate arrays (FPGAs) can help the broadcast industry achieve the highest levels of performance and systems integration at the lowest power for High Definition (HD) and beyond. Altera is in Hall 10, Stand #10.A10 where … Read More → "Altera Demonstrates Broadcast Solutions at IBC 2013"

New voltage regulator from Ericsson delivers digital dynamic-loop-compensation

September 10, 2013

Advanced POL module enables designers to achieve high performance without compromising on dynamic response
First auto-compensated digital point-of-load regulator is based on ‘state-space’ or ‘model-predictive’ control, reducing cost and time-to-market while increasing flexibility
Land-grid-array footprint improves quality, reliability and manufacturability
Low bias current contributes to higher efficiency

Ericsson has introduced a new 3E* DC-DC regulator, the BMR461, that is the first 12 x 12 x 8mm 12A digital point-of-load (POL) module to combine Dynamic Loop Compensation (DLC), low-bias current technology, advanced energy-optimization algorithms to reduce energy consumption, and a land-grid-array ( … Read More → "New voltage regulator from Ericsson delivers digital dynamic-loop-compensation"

Xilinx and its Ecosystem Expand All Programmable Abstractions to Empower More Designers and Accelerate Productivity up to15X

September 10, 2013

SAN JOSE, Calif., September 10, 2013 – Xilinx, Inc. (NASDAQ: XLNX) today announced the All Programmable Abstractions initiative to improve productivity of hardware designers and to empower systems and software developers to directly leverage All Programmable FPGA, SoCs, and 3D ICs. Xilinx and its ecosystem Alliance members including MathWorks® and National Instruments® now support a combination of software, model, platform, and IP-based design environments. These environments enable high-level graphical and text-based programming languages such as C, C++, SystemC, and will soon support OpenCL™ (Open Computing Language) with advanced automation technology that translates these languages into optimized implementations. These software … Read More → "Xilinx and its Ecosystem Expand All Programmable Abstractions to Empower More Designers and Accelerate Productivity up to15X"

Cadence Launches Palladium XP II Verification Platform and Enhanced System Development Suite

September 10, 2013

SAN JOSE, CA–(Marketwired – September 09, 2013) – Cadence Design Systems, Inc. (NASDAQ: CDNS)

Highlights:

Palladium XP II platform delivers 2X increase in verification productivity, resulting in up to four months faster time to market
Enhanced System Development Suite delivers up to 60X speed-up for embedded OS verification and 10X performance increase in hardware/software verification

In a move to further reduce time to market for both semiconductor and system manufacturers, Cadence Design Systems, Inc. (NASDAQ: Read More → "Cadence Launches Palladium XP II Verification Platform and Enhanced System Development Suite"

Zuken makes electrical designs come alive and identifies errors

September 10, 2013

10 September 2013 – Munich, Germany and Westford, MA, USA – Zuken announces a new product for electrical design that identifies errors at the development stage and avoids costly iterations. E³.eCheck – part of Zuken’s E³.series industry-leading electrical and fluid CAD software – automatically ensures the schematic is functionally accurate and that wires and fuses are within the acceptable tolerances. The design analysis runs in real-time and replaces time-consuming manual checks.

“E³.eCheck represents an advancement in the tools available for electrical engineering of … Read More → "Zuken makes electrical designs come alive and identifies errors"

Hathway Selects STMicroelectronics to Power its High-Definition Set-Top Boxes

September 10, 2013

Geneva, September 10, 2013 – STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the spectrum of electronics applications and a top player in ICs for digital TVs and set-top boxes (STB), today announced that Hathway, a leading cable Multi-System Operator (MSO) in India with more than 6 million digital subscribers has chosen ST’s highly integrated systems-on-chips (SoC) to power two of its advanced high-definition (HD) set-top boxes. ST’s STiH273 (Palma) drives Hathway’s newest HD entry-level set-top box … Read More → "Hathway Selects STMicroelectronics to Power its High-Definition Set-Top Boxes"

TSMC and Synopsys Extend Custom Design Collaboration into 16-nm

September 9, 2013

MOUNTAIN VIEW, Calif., Sept. 8, 2013 /PRNewswire/ —

Highlights:

TSMC certifies Laker custom design solution for TSMC 16-nm FinFET process Design Rule Manual (DRM) v0.5
Laker features for TSMC 16-nm v0.5 iPDK include support of complex FinFET abutment rules, double-patterning, middle end-of-line (MEOL) layers and other requirements of advanced-node design
TSMC and Synopsys continue support for iPDKs to foster innovation in custom design

Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced … Read More → "TSMC and Synopsys Extend Custom Design Collaboration into 16-nm"

Barco Silex releases Multi-Channel Ultra HDTV 8K JPEG 2000 encoder and decoder cores

September 9, 2013

Louvain-la-Neuve, Sept. 6, 2013 – Barco Silex, the leading provider of JPEG 2000 compression IP cores and solutions, announced today the release of a new range of single-chip, multi-channel 8K UHDTV JPEG 2000 cores. The cores have been implemented on the 28nm FPGA’s and SoC’s of Altera and Xilinx.

“This new range of ultra-high resolution JPEG 2000 cores fitting in a single FPGA or SoC device are facilitating manufacturers to develop future-proofed solutions for UHDTV”, said Jean-Marie Cloquet, Manager of the image processing division of Barco Silex. “Thanks to the flexible and scalable architecture of our cores, we … Read More → "Barco Silex releases Multi-Channel Ultra HDTV 8K JPEG 2000 encoder and decoder cores"

Cadence Announces Industry’s First Verification IP for HDMI 2.0

September 9, 2013

SAN JOSE, CA–(Marketwired – September 06, 2013) – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the availability of the industry’s first verification IP (VIP) supporting the new HDMI 2.0 specification. This VIP enables designers to quickly and thoroughly verify that their systems-on-chip (SoCs) conform to the HDMI 2.0 specification, accelerating ramp-up to mass production. The Cadence VIP for HDMI 2.0 supports all major logic simulators, verification languages, and methodologies including the Universal Verification Methodology (UVM).

“The HDMI 2.0 verification IP provided … Read More → "Cadence Announces Industry’s First Verification IP for HDMI 2.0"

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