SANTA CLARA, Calif., May 19, 2015 – Applied Materials, Inc. today announced its Applied Endura® Cirrus HTX PVD* system with breakthrough technology for patterning copper interconnects at 10nm and beyond. As chip features continue to shrink, innovations in hardmask are required to preserve the pattern integrity of tightly packed, tiny interconnect structures. With the introduction of this technology, Applied enables scaling of the TiN* metal hardmask – the industry’s material of choice – to meet the patterning needs of copper interconnects in advanced microchips.

“Precision engineering of metal hardmask films is key to addressing the patterning challenges for advanced interconnects,” said … Read More → "Applied Materials’ Breakthrough Patterning Hardmask Enables Copper Interconnect Scaling"

IEEE IITC, Grenoble, (France) – May 20, 2015 – Today, at the IEEE IITC conference, nano-electronics research center imec and Tokyo Electron Limited (TEL) presented a direct Cu etch scheme for patterning Cu interconnects. The new scheme has great potential to overcome resistivity and reliability issues that occur while scaling conventional Cu damascene interconnects for advanced nodes.

Aggressive scaling of damascene Cu interconnects leads to a drastic increase in the resistivity of the Cu wires, due to the fact that grain size is limited by the damascene trenches, which results in increased grain boundary and surface scattering. Additionally, the grain boundary … Read More → "Imec and Tokyo Electron Demonstrate Electrical Advantages of Direct Cu Etch Scheme for Advanced Interconnects"