IRT Nanoelec Partners Achieve 3D Chip-stacking Technology & 3D Network-on-chip Framework for Digital Processing
GRENOBLE, France – July 09, 2015 – IRT Nanoelec, an R&D consortium focused on Information and Communication Technologies (ICT) using micro- and nanoelectronics, and its partners CEA-Leti, STMicroelectronics and Mentor Graphics have realized an innovative 3D chip called “3DNoC” to demonstrate the use of 3D stacking technology in scalable, complex digital systems-on-chip (SoCs).
The 3DNoC chip is based on a 2D die that can be used in a stand-alone applicative mode, and also in a 3D stack with several dice, to multiply the processing performance of the system. The project’s complete demonstration platform shows both the simulated and … Read More → "IRT Nanoelec Partners Achieve 3D Chip-stacking Technology & 3D Network-on-chip Framework for Digital Processing"

