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STMicroelectronics Certifies Cryptographic Library for STM32 Microcontrollers According to US Security Standards

Geneva, July 13, 2016 – STMicroelectronics has successfully certified its cryptographic library for STM32 microcontrollers according to the US Cryptographic Algorithm Validation Program (CAVP), helping customers prove the security of their … Read More → "STMicroelectronics Certifies Cryptographic Library for STM32 Microcontrollers According to US Security Standards"

Intel Custom Foundry Certifies Cadence Implementation and Signoff Tools for 10nm Tri-Gate Process

San Jose, Calif., July 13, 2016 ?Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its implementation and signoff tools have achieved certification on the Intel® third-generation 10nm tri-gate process for customers of Intel Custom Foundry. Intel Custom Foundry utilized a PowerVR GT7200 graphics processing unit (GPU) from Imagination Technologies as part of the certification process.

The tool certification and enablement provide Intel Custom Foundry customers with a complete and integrated system-on-chip (SoC) design flow. Cadence® tools in the flow include:

? Innovus? Implementation System: This massively parallel physical implementation system utilizes GigaPlace? placement technology, GigaOpt? optimization technology … Read More → "Intel Custom Foundry Certifies Cadence Implementation and Signoff Tools for 10nm Tri-Gate Process"

Synopsys TetraMAX II Speeds Test Generation for STMicroelectronics SoC Designs

MOUNTAIN VIEW, Calif., July 12, 2016 /PRNewswire/ —

Highlights:

  • Evaluation of TetraMAX II demonstrated an order of magnitude speedup in runtime
  • Achieves significant test-pattern-count reduction without impacting test coverage

Synopsys, Inc. (Nasdaq: SNPS), today announced that STMicroelectronics is seeing significantly faster test pattern generation runtime and reduced number of patterns with TetraMAX® II ATPG. STMicroelectronics faces the challenges of increasing complexity and shrinking time-to-market schedules for their system-on-chip (SoC) designs. To meet these challenges, STMicroelectronics requires fast turn-around time (TAT) for generating high-quality manufacturing test patterns. … Read More → "Synopsys TetraMAX II Speeds Test Generation for STMicroelectronics SoC Designs"

Leti Develops 3D Network-On-Chip to Improve High-Performance Computing

SAN FRANCISCO – July 12, 2016 – Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.?

Leti researchers, working in the frame of IRT Nanoelec, boosted computing power and slashed energy consumption by stacking chips on top of … Read More → "Leti Develops 3D Network-On-Chip to Improve High-Performance Computing"

Toshiba Plans Deployment of Synopsys TetraMAX II on Upcoming SoC Design

MOUNTAIN VIEW, Calif., July 12, 2016 /PRNewswire/ —

Highlights:

  • Thorough evaluation of TetraMAX II demonstrated significant reductions in both pattern count and runtime without impacting test coverage
  • TetraMAX II was up and running in Toshiba’s flow with minimal effort
  • Toshiba is planning to deploy TetraMAX II and its advanced power-aware ATPG capabilities on their upcoming SoC design.

Synopsys, Inc. (Nasdaq: SNPS), today announced that Toshiba has confirmed that Synopsys TetraMAX® II ATPG can significantly accelerate test pattern generation and reduce manufacturing test time and cost. … Read More → "Toshiba Plans Deployment of Synopsys TetraMAX II on Upcoming SoC Design"

IRT Nanoelec and CMP Announce World’s First Multi-Project Wafer Service with Silicon Photonics on 310nm SOI Platform

GRENOBLE, France – 11 July, 2016 – IRT Nanoelec, an R&D consortium focused on information and communication technologies (ICT) using micro and nanoelectronics, and CMP, Circuits Multi-Projets®, a service organization in ICs and MEMS prototyping and low volume production, today announced the IC industry’s first multi-project wafer (MPW) process for fabricating silicon-photonics devices on a 310nm silicon on insulator (SOI) platform. Read More → "IRT Nanoelec and CMP Announce World’s First Multi-Project Wafer Service with Silicon Photonics on 310nm SOI Platform"

Keysight Technologies Introduces Industry’s First All-in-One Software for R&D Engineers Designing, Evaluating 5G Candidate Waveforms

Highlights:

  • Simplifies the building of test systems with wideband channels at the transmitter, receiver, or both
  • Facilitates complex calibration of RF to millimeter-wave measurement systems and creates task-based test setup guidance—from signal creation to measurement
  • Generates and analyzes 5G candidate waveforms to ensure accurate and repeatable measurements

SANTA ROSA, Calif., July 11, 2016 – Keysight Technologies, Inc. (NYSE: KEYS) today introduced its Signal Optimizer software—the industry’s first and only all-in-one software for calibration, signal creation and signal analysis of 5G candidate waveforms. By simplifying calibration and the critical design … Read More → "Keysight Technologies Introduces Industry’s First All-in-One Software for R&D Engineers Designing, Evaluating 5G Candidate Waveforms"

Imec and Synopsys Collaborate on Interconnect Resistivity Model to Enable Early Screening of Interconnect Technology Options at Advanced Nodes

MOUNTAIN VIEW, Calif., July 11, 2016 — World-leading nano-electronics research center imec and Synopsys, Inc. (NASDAQ: SNPS) today announced an interconnect resistivity model to support the screening and selection of alternative interconnect metals and liner-barrier materials at the 7nm node and beyond. With the continued scaling of advanced process nodes, the impact of parasitic interconnect resistance on the switching delay of standard cells rises considerably. The new model developed through this collaboration enables the evaluation of interconnect material and process options through simulations in the early stages of technology development, when wafer data is not available, and in the process optimization … Read More → "Imec and Synopsys Collaborate on Interconnect Resistivity Model to Enable Early Screening of Interconnect Technology Options at Advanced Nodes"

Small Footprint Secondary-Side MOSFET Driver from Diodes Incorporated Reduces BOM Cost in 5V to 12V Power Supplies

Plano, Texas –July 12th, 2016 – The APR345 secondary-side MOSFET driver introduced by Diodes Incorporated delivers the smallest size, lowest BOM cost solution for synchronous rectification in 5V to 12V power supplies. This device is suitable for line-powered adapters and chargers for consumer products such as smartphones and tablets, PVRs and IPTV boxes, cable and xDSL modems, datacom equipment and other portable consumer/home appliances. This device provides a high-performance power conversion solution for standby and auxiliary power supplies.

In conjunction with an external MOSFET for greater design flexibility, the APR345 driver provides synchronous secondary-side rectification … Read More → "Small Footprint Secondary-Side MOSFET Driver from Diodes Incorporated Reduces BOM Cost in 5V to 12V Power Supplies"

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