eSilicon at TSMC OIP 2017: High-Performance 7FF IP Platform and 7FF HBM2/LL HBM Combo PHY
eSilicon, an independent provider of FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions, will deliver several presentations in booth 807 at the 2017 TSMC OIP Ecosystem Forum in Santa Clara, California at the Santa Clara Convention Center on September 13, 2017.
High-Performance Networking and Computing 7FF IP Platform
Highly differentiating TCAM and memory compilers, I/O libraries and 56G SerDes for high-performance, high-bandwidth applications.
8:30 AM & 12:40 PM, booth 807
7FF Combo PHY: High-Bandwidth Memory Gen2 and Low-Latency … Read More → "eSilicon at TSMC OIP 2017: High-Performance 7FF IP Platform and 7FF HBM2/LL HBM Combo PHY"

