Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
Highlights:
• Cadence digital, signoff and custom/analog tools achieve latest DRM and SPICE certifications for TSMC 5nm and 7nm+ process technologies
• Early customers using Cadence tools for 5nm design projects ranging from initial bring-up to full production development; customers in production with 7nm+ projects
SAN JOSE, Calif., October 1, 2018—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs. As part of the collaboration, the Cadence® digital, signoff and custom/analog tools have … Read More → "Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation"

