Sunnyvale, CA, December 5, 2018 – Zeno Semiconductor, a Silicon Catalyst Portfolio Company, demonstrated the scalability of its novel 1-transistor/2-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology to FinFET technology node at the IEDM Conference. The results from 14nm and 16nm FinFET technology nodes from multiple foundries follow previous implementation of Bi-SRAM technology in 28nm technology node.

Zeno’s 1-transistor/2-transistor Bi-SRAM uses a single transistor as the memory bitcell and is therefore 3x-5x smaller than conventional SRAMs which use 6-transistor bitcells (6T-SRAM). Another key disclosure is that the Bi-SRAM technology can … Read More → "Zeno Demonstrates Scalability of World’s Smallest SRAM Bitcell Technology to FinFET Technology Node at IEDM Conference"

SAN FRANCISCO (USA), DECEMBER 3, 2018 — At this week’s 2018 IEEE International Electron Devices Meeting (IEDM), imec, the world-leading research and innovation hub in nano-electronics and digital technology, reports significant progress in process enabling the introduction of gate-all-around (GAA) transistors with vertically stacked nanowires and nanosheets for the N3 technology node. Results include improved Si GAA devices, better understanding of strain engineering in Ge nanowire pFETs, and a comprehensive understanding of reliability and degradation mechanisms of nanowire FETs.

GAA MOSFETs are promising candidates to extend the gate length … Read More → "Imec Improves Performance and Understanding of Stacked Nanowire Gate-All-Around Transistors for N3 and Beyond"

SAN FRANCISCO (USA), DECEMBER 3 , 2018 — This week, at the 2018 IEEE International Electron Devices Meeting (IEDM), imec, the world-leading research and innovation hub in nanoelectronics and digital technologies, presents the first power-performance-area comparison between SRAM- and SST-MRAM-based last-level caches at the 5nm node. The analysis, based on design-technology co-optimization and silicon verified models, reveals that STT-MRAM meets the performance requirements for last-level caches in the high-performance computing domain. Moreover, for larger memory densities, significant energy gains are found for SST-MRAM compared to SRAM.  

The increased complexity of … Read More → "Imec Demonstrates the Feasibility of Introducing SST-MRAM as a Last-Level Cache at the 5nm Technology Node"