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EnSilica and Codasip announce strategic partnership to bring CHERI cybersecurity to automotive, critical national infrastructure, defence and aerospace applications

Oxfordshire, United Kingdom and Munich, Germany, – September 22, 2025: EnSilica, a fabless supplier of mixed-signal and digital ASICs, and Codasip, a provider of functionally-safe and cyber-resilient RISC-V CPUs, announces a strategic partnership to enable custom ASICs incorporating CHERI (Capability Hardware Enhanced RISC Instructions), Post-Quantum Cryptographic (PQC) acceleration, and advanced system-level security and safety features. These will serve industrial, automotive, critical national infrastructure, including defence and aerospace applications.
CHERI represents a transformative hardware security architecture designed to mitigate memory safety vulnerabilities, one of the most significant sources of modern cyberattacks, and provides fine-grained compartmentalisation to increase software robustness and resilience.
EnSilica will use Codasip’s portfolio of 32-bit and 64-bit CHERI RISC-V processors as the foundation for developing customer-specific System-on-Chip (SoC) integrated circuits. These secure platforms will integrate processing, PQC and classical encryption hardware, and tailored analogue and digital functionality to meet the precise requirements of the end application.
Ian Lankshear, CEO of EnSilica said: “Cybersecurity has become a defining challenge for automotive, industrial and defence systems, with attacks growing in scale and sophistication. This partnership positions EnSilica at the forefront of delivering cyber-resilient chips that combine CHERI’s hardware-enforced memory safety with post-quantum cryptography. By building on Codasip’s advanced CHERI RISC-V processors, we can offer customers complete, application-specific ASIC solutions with security and functional safety designed in from the ground up. We are excited to work with Codasip to bring this next generation of trusted silicon to market.”
Dr Ron Black, CEO of Codasip added: “The partnership will help to unlock the full potential or our leading-edge 32-bit and 64-bit CHERI RISC-V CPUs. Developed in line with ISO 26262 functional safety and ISO 21434 cybersecurity standards, our processors come with a complete ecosystem including CHERI toolchain, CHERI Linux, and CHERI RTOSes. By combining these with EnSilica’s ASIC expertise, we can accelerate the adoption of CHERI-based security in mission-critical applications.”
 
About EnSilica plc
EnSilica is a leading fabless design house focused on custom ASIC design and supply for OEMs and system houses, as well as IC design services for companies with their own design teams. The company has world-class expertise in supplying custom RF, mmWave, mixed signal and digital ICs to its international customers in the automotive, industrial, healthcare and communications markets. EnSilica has a track record in delivering high-quality solutions to demanding industry standards. The company is headquartered near Oxford, UK and has design centres across the UK and in Bangalore, India, Porto Alegre and Campinas, Brazil and Budapest, Hungary. More information: www.ensilica.com.
About Codasip Gmbh
 
Codasip is the leading European processor technology company enabling system-on-chip developers to differentiate their products for competitive advantage. Customers leverage the transformational potential of the open RISC-V ISA in a unique way through Codasip’s Custom Compute Electronic Design Automation offering: Codasip Studio tool and a fully open architecture licensing model combine with a comprehensive range of processor IP built on a foundation of safety ands and can be easily customized with zero risk on verification and validation. The company is proudly European and serves a global market, where billions of devices are already enabled by Codasip technology.

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