Munich, Germany – March 9th, 2021 – Codasip, the leading supplier of customizable RISC‑V processor IP, announced three commercially licensed add-ons to the Western Digital SweRV Core® EH1. The add-ons enable the SweRV Core EH1 to be designed into a wider range of applications.
The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. Codasip is now offering three add-on options to EH1:
- A floating-point unit (FPU) that supports the RISC-V single precision [F] and double precision [D] instructions.
- A data cache with configurable size, associativity, and cache lines. It can be configured with either AXI or AHB-Lite interfaces.
- Additional instructions for bit manipulation which can be beneficial for error detection/correction, DSP, and security algorithms.
“The development of business models around open-source processor cores is following a similar path to the software world,” explained Karel Masařík, CEO of Codasip. “Commercially licensed add-ons to open-source software, such as IBM’s database software and middleware, are offered as paid options to Linux. We are providing three options to SweRV Core EH1 on a similar basis.”
The SweRV Core EH1 is a powerful, two-way superscalar, 32-bit embedded processor core with a 9-stage pipeline. The SweRV Core EH1, along with the EH2 and EL2 cores, was developed by Western Digital. The deployment of these cores with commercial EDA tools and SDK is supported by Codasip’s SweRV Core Support Package Pro. A free version is available through CHIPS Alliance on GitHub.
The SweRV Core EH1, EH2, and EL2 are available to the open-source community through CHIPS Alliance, an open-source development organization which seeks to provide a barrier-free environment to allow collaboration for open-source software and hardware code. The EH1 has an optional 4-way set-associative instruction cache and optional instruction and data closely-coupled memories.
