SAN JOSE, Calif., June 2, 2016—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Hitachi, Ltd. (TSE:6501) has adopted a Cadence® Analog Mixed-Signal (AMS) model-based methodology and tools to shorten the verification cycle for one of its largest mixed-signal design projects. By upgrading its previous transistor-level methodology to a model-based methodology, Hitachi successfully accelerated mixed-signal verification for this project by 160X and reduced full-chip simulation time to 30 minutes. The results were achieved by comparing the transistor-level and the model-based methodology on the same four CPUs. The significant reduction in the verification cycle time provided Hitachi with the ability to meet time-to-market goals for designs that integrate both analog and digital functions.
With its previous transistor-level methodology, Hitachi predominantly relied on block-level verification followed by tuning analog-digital interfaces to ensure full-chip functionality, which typically required multiple, costly iterations. By using a Verilog-AMS real number modeling and simulation flow supported by a full set of Cadence tools—Virtuoso® Analog Design Environment (ADE), Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Virtuoso AMS Designer and Incisive® Enterprise Simulator—Hitachi reduced iterations and met its accuracy requirements, ultimately speeding time to market.
For more information on the Cadence tools, please visit http://www.cadence.com/news/hitachi.
“We’ve had a trusted partnership with Cadence for many years, and our effective collaboration produced a design environment that significantly improved our productivity and helped us achieve design goals,” said Satoshi Ueno, director of Design Engineering Second Department, Technology Development Operation 1, IT Platform Products Management Division, Information and Communication Technology Business Division at Hitachi, Ltd. “Cadence has the behavioral modeling expertise, methodology and tools that we needed to reduce our verification time and enable us to thoroughly verify our design—not just at the block level, but at the full-chip level, which includes sensitive analog-digital interfaces. The gains achieved have had a positive impact on our business, and we also plan to evaluate the Cadence tools and methodology for medical applications and various other system applications.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at http://www.cadence.com.
