SAN JOSE, CA–(Marketwired – June 20, 2013) – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its participation at PCI-SIG Developers Conference 2013, an annual conference that provides comprehensive training on all aspects of the PCI (peripheral component interconnect) standard.

WHAT:

Visitors to the Cadence booth (#9) can participate in the following demonstrations:

• Low-power PCIe controller and PHY
• Mobile PCIe controller and MIPI M-PHY
• PCIe with TripleCheck IP Validator
• Chip-package-board design and analysis

Cadence will deliver papers at two conference sessions:

• “Testing and Verification of NVMe PCIe devices” – Moshik Ruben (10:30-11:30 am on Tuesday, June 25)
• “MPCIe implementation case study” – Martin James (3:30 – 4:30 pm on Tuesday, June 25)

WHEN:

June 25-26, 2013

WHERE:

Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054