The SSIC IP provides low power, high speed chip to chip interconnect which leverages existing investments in USB software and system investments.  High performance and reduced power are achieved by using the MIPI® M-PHY  as the physical layer interface. Leveraging the MIPI M-PHY power management, the SSIC interface lowers the active power and idle power. The SSIC adapter layer IP is optimized for power, area, and EMI robustness for embedded inter-chip interfaces.

“We are known for our strong position in the SD/eMMC and MIPI IP markets, but most customers are not aware of our commitment to offering superior support”, said Andrew Haines, Vice President of worldwide Marketing at Arasan. “Support at Arasan is provided by development engineers working on the product, guaranteeing the customer will be communicating with someone who has the highest level of knowledge. This level of support is standard, regardless of where the support request is coming from.”

Arasan’s Superspeed Inter-Chip controller is a PHY adapter layer that provides a bridge between a USB 3.0 Host, Device or OTG controllers’ PIPE interface and the MIPI M-PHY RMM I interface. The Arasan USB 3.0 SSIC controller interfaces directly to Arasan’s MIPI M-PHY IP to implement the SSIC adaptation to the USB 3.0 PIPE interface.

The Arasan USB 3.0 SSIC controller is compliant with the “Super Speed Inter-Chip” supplement to the USB revision 3.0 specification, version 1.0 and the MIPI M-PHY specification revision 3.0-r.03 and provides an effective data rate of up to 5.0 Gbps per lane over 1 to 4 lanes of M-PHY. The Arasan USB 3.0 SSIC controller interfaces to the USB 3.0 Device or Host controller with PIPE3 interface at 8/16/32-bit data width. 

Availability

The Arasan SSIC controller is available now and is licensed as RTL or as GDSII when delivered with Arasan’s Type 1 M-PHY.   The deliverables include verification IP and world-wide support.