Henderson, NV – February 25, 2013 – Aldec, Inc., recently announced the launch of Fast Track™ ONLINE, a convenient, online training portal that is available at no cost to the design verification community. The premier training, Fast Track™ to UVM ONLINE, introduced hardware designers familiar with Design Subset of SystemVerilog into the brave, new world of Universal Verification Methodology (UVM).
Now, Aldec has added Fast Track™ to Assertions, created to allow hardware designers to easily enter the world of properties, assertions and covers. All terms and ideas are clearly explained with one module devoted to explanation of Temporal Logic – the mathematical background of assertions. The practical examples of assertions and covers are presented side-by-side in VHDL (PSL) and SystemVerilog (SVA).
This convenient, online training portal is available at no cost to all aldec.com registered users. Signing up for an Aldec account is easy and provides one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources.
To get started, visit http://www.aldec.com/en/onlinetraining.
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
