ACTON, MASS. –– May 24, 2012 –– Carbon Design Systems® Inc., a leading supplier of virtual prototype and secure model solutions, and Cadence Design Systems® announced today availability of a Carbon Performance Analysis Kit (CPAK) to accelerate the intellectual property (IP) benchmark process.
The CPAK incorporates a Cadence double data rate (DDR3) Memory Controller together with an ARM® Cortex™-A9 MPCore™ processor, and industry-standard benchmarks, such as those from EEMBC®.
“Optimization of the processor to memory datapath plays a key role in the development of many leading-edge SoCs,” remarked Rick Lucier, president and chief executive officer at Carbon. “By partnering with Cadence to deploy this CPAK, we are enabling engineers to be more productive by benchmarking the same day they download the package from Carbon IP Exchange.”
“Being able to quickly demonstrate the value and ease of use of our memory controller models is a great aid to our customers,” stated Vishal Kapoor, vice president of marketing, SoC Realization Group at Cadence. “This Performance Analysis Kit bypasses any traditional setup issues and enables engineers to be productive immediately.”
“The Carbon/Cadence Performance Analysis Kit executing CoreMark highlights the important role that industry standard benchmarks can play in the IP selection process,” added Markus Levy, president of EEMBC.
“ARM power-efficient technology is at the heart of many products, ranging from embedded microcontroller applications to servers, network infrastructure and smart connected devices,” commented Joe Convey, Director of Design Enablement, ARM. “Reference implementations, such as the Carbon/Cadence Performance Analysis Kit, are important tools that allow ARM Partners to innovate more easily by quickly understanding capabilities of the Cortex-A9 processor.”
About the Platform
The Carbon/Cadence offering is the latest addition to the library of Carbon Performance Analysis Kits available from Carbon’s IP Exchange web portal (www.carbonipexchange.com). This platform features an ARM Cortex-A9 processor and a Cadence DDR3 memory controller, along with configurable models for the interconnect fabric, DDR3 memory and memory PHY.
In addition, multiple configurable traffic generators are included as producers and consumers to model additional bus traffic. Included in the system is a software package that includes, among other tests, the CoreMark benchmark from EEMBC. The CPAK executes in Carbon’s SoCDesigner Plus virtual prototype environment that delivers a rich suite of analysis and visualization tools.
Availability
The Carbon/Cadence CPAK is available now from Carbon’s IP Exchange web portal: www.carbonipexchange.com. The ported CoreMark benchmarking software is available from www.coremark.org.
Carbon and Cadence are part of the ARM Connected Community®, a global network of over 900 companies with access to a wide variety of resources and aligned to provide optimized solutions based on the ARM architecture.
About Carbon Design Systems
Carbon offers the industry’s only unified virtual prototype solution along with the leading solution for accurate IP model creation. Carbon virtual platforms can execute at 100s of MIPS and with 100% accuracy to enable application software development, detailed architectural analysis and secure IP model distribution. Carbon’s solutions are based on open industry standards, including SystemC, IP-XACT, Verilog, VHDL, OSCI TLM, MDI, CASI, CADI and CAPI. Carbon’s customers are systems, semiconductor, and IP companies that focus on wireless, networking, and consumer electronics. Carbon is headquartered at 125 Nagog Park, Acton, Mass., 01720. Telephone: (978) 264-7300. Facsimile: (978) 264-9990. Email: info@carbondesignsystems.com. Website: www.carbondesignsystems.com.
