SANTA CLARA, Calif., April 24, 2012 /PRNewswire/ — Achronix Semiconductor Corp. today announced the details of the Speedster22i HD and HP product families, the first FPGAs to be built on the Intel 22nm technology process. Speedster22i FPGAs are the industry’s only application targeted, high-end FPGAs and consume half the power at half the cost of 28nm, high-end FPGAs.
Speedster22i devices are the first FPGAs to include integrated end-to-end, hard IP protocol functions targeted for communications and test applications. The Speedster22i hard IP includes the entire I/O protocol stack for 10/40/100 Gigabit Ethernet, Interlaken, PCI Express gen1/2/3 and memory controllers for 2.133Gbps DDR3. In other FPGAs, these functions are built in the programmable fabric making timing closure challenging and requiring the use of up to 500,000 equivalent look-up-tables (LUTs) from the programmable fabric. This adds a large cost and power consumption overhead to the traditional FPGA design, which in Speedster FPGAs is basic connectivity. Additionally, the embedded hard IP eliminates the cost of purchasing, integrating and testing these functions as soft IP.
“We worked closely with leading companies in the communications and test segments to design our FPGAs to meet their performance, power, and cost requirements” said Robert Blake, Achronix’s President and CEO. “The combination of Intel’s 22nm process leadership and our innovation in both the core fabric and embedded hard IP for targeted applications means that our customers will have a high-end FPGA solution that is half the power and half the cost of competitive FPGAs.”
“Part of our differentiating strategy is to integrate best-in-class, silicon-proven IP,” said John Lofton Holt, Achronix’s founder and Chairman of the Board. “For example, beyond the dramatic power and performance advantages afforded by Intel’s 22nm process, our Speedster22i devices also leverage an entire portfolio of industry-leading I/O, core and packaging IP that was developed by Intel. This helped us achieve previously unreachable levels of performance and signal integrity, and at the same time, reduce our development time and development costs.”
Two Product Families for Different Target Applications
Speedster22i has 2 product families, HD and HP that share the same I/O functionality and hard IP. Both families leverage the Achronix CAD Environment (ACE) design platform, which provides a seamless and familiar tool environment for designers.
HD Family: The HD FPGAs are a synchronous based family that offers the combination of the highest density FPGA with the lowest power consumption. There are 4 members in the HD family with the largest device having 1.7 million effective LUTs and 144 Mb of embedded RAM. Additionally, with up to sixteen 28-Gbps SerDes, sixty-four 12.75-Gbps SerDes and 960 general purpose 2.133-Gbps I/O, the HD family offers the industry’s highest I/O bandwidth, which is critical for high end switch and bridging applications.
HP Family: The HP FPGAs uses Achronix’s patented picoPIPE™ self-timed architecture and operates at up to 1.5 GHz and is 3x to 4x faster than synchronous based FPGAs. Speedster22i HP FPGAs are designed to achieve maximum performance for feed forward data flow and DSP applications. There are 2 members in the HP family with the largest device having 250 thousand LUTs and 64 Mb of embedded RAM.
Power Advantage
For the targeted applications, the embedded hard IP consumes up to 90% less power than implementing the same functionality in the programmable fabric of general purpose FPGAs. Additionally, innovations supplied by Intel’s 22nm FinFET process consume 50% less power and are nearly 40% faster than transistors built on 28nm planar processes. For the HD devices, these combined factors result in up to 50% less total power consumption than mainstream FPGAs.
Robust 3rd Generation of ACE Design Tools Available Today
Both the HD and HP families are supported in Achronix’s mature and easy-to-use ACE design software version 4.2 which is now available. ACE is the only FPGA design tool built on the industry standard Eclipse Foundation open source platform making ACE easy to learn for Engineers who have worked on any other design tools built on the Eclipse platform.
“Our application targeted FPGAs offer a clear cost and power advantage, but our customers are also focused on design productivity,” said Steve Mensor, Achronix’s Vice President of Marketing. “Our powerful and robust ACE design tools, now in the fourth generation, make timing closure easy. The combination of our powerful design tools, core performance advantage and embedded hard IP in most cases make timing closure push button.”
Early Access Program
Achronix is focused on the success of its customers. To ensure the Speedster22i has a smooth ramp to production and to ensure ample support for its early customers, Achronix has an early access program to help customer seamlessly migrate from traditional FPGAs to Speedster 22i. The early access program includes evaluation boards, onsite training and technical support. Customers should contact Achronix to obtain more information about the early access program.
Device Availability
Engineering samples of the HD1000 will begin shipping in Q3 2012. The HD1000 is the industry’s largest FPGA with over 1 million effective LUTs and 84 Mb of embedded RAM. The remaining HD and HP devices will be rolled out in the next 12 months.
About Achronix Semiconductor
Achronix Semiconductor is a privately held fabless corporation based in San Jose, California. Achronix builds application targeted field programmable gate arrays (FPGAs). Achronix has sales offices and representatives in the United States, Europe, and China, and has research and design offices in Ithaca, N.Y., and Bangalore, India. Find out more at http://www.achronix.com.
