COPENHAGEN, Denmark, March 14th, 2012 – Teklatech®, an industry leader in EDA solutions for achieving faster power integrity and noise closure in System-on-Chip (SoC) designs, today announced the release of version 3.2 of its FloorDirector® tool. FloorDirector 3.2 combines high-performance power rail analysis with its signature Dynamic Power Shaping™ capabilities, to enable a powerful Rail-Aware Optimization™ (RAO) solution.
The RAO-enabled design flow allows backend designers of SoC devices to perform advanced, cell-based power rail analysis, and integrates this tightly into FloorDirector’s dynamic power optimization engine. The existing engine is used by design teams today to achieve best-in-class dynamic power integrity, for fewer re-spins, higher yield, lower area and robust manufacturability. The new flow lets them set dynamic IR-drop optimization targets directly on the power grid, for improved accuracy.
Power noise and dynamic rail analysis is increasingly important”, says Dr. Tobias Bjerregaard, CEO and Founder of Teklatech. “Over the past 5 years, dynamic power integrity sign-off has become truly mainstream. The vast majority of IC design groups have a sign-off solution in place. But analysis alone is not enough. We see a clear trend in the semiconductor industry, that designers of the most demanding designs are now seeking automated solutions.”
As the shift from 65nm to 45nm picked up, issues uncovered during power network analysis became too challenging to handle by ECO and manual fixes. And at 28nm and beyond, automated solutions are absolutely necessary, to keep up with design requirements. There is a need to take optimization technologies in use earlier in the flow, to guide the physical implementation intelligently from the start of the process, by physical-level awareness during the SoC Realization phase. This is what FloorDirector does.
“There are providers of EDA tools that claim to be able to reduce current peaks. With years of focus, and dedicated R&D and support resources, in this field, Teklatech is several generations ahead of that simple goal,” says Christian Petersen, VP of Worldwide Sales at Teklatech. “FloorDirector 3.2 provides a range of advanced features used to achieve the best possible dynamic power integrity optimization for a given design under given constraints. It is possible to shape the current pulse according to its frequency spectrum, to target an optimization according to actual cell placement and the power delivery network, to handle even the most difficult designs by making intelligent trade-offs in the optimization, e.g. regarding number of hold-time or clock tree buffers, and more. And all this can be done in a mix-and-match fashion, and across multiple modes and corners.”
Coupled with FloorDirector’s Frequency Domain Optimization™ (FDO) capabilities, RAO becomes a particularly powerful feature. This combination enables an optimization towards a low dynamic voltage drop peak directly in the on-chip power network, together with a softening of the current slope across the supply pads, leading to greatly improved L-drop (di/dt noise) across the inductive package leads.
The new FloorDirector release further extends the unique capabilities of Teklatech’s world-leading Dynamic Power Shaping solution. Together with Rail-Aware Optimization, FloorDirector 3.2 boosts usability with a flexible yet simple to adapt reference flow, aimed at enabling fast technology adoption across multiple design teams in large organizations. In unison with Teklatech’s world class support, design teams are enabling power integrity optimization in their flows, without a steep learning curve.
FloorDirector 3.2 is available as of today, to new and existing customers.
About Teklatech
A technology visionary and industry pioneer, Teklatech provides targeted IC design solutions to the semiconductor industry. With innovations in dynamic current optimization techniques to reduce IR-drop, EMI and substrate noise, Teklatech is focused on helping its customers meet the stringent demands of next-generation semiconductor products. Teklatech’s patented technologies enable companies to achieve faster and less expensive backend convergence, eliminate costly silicon re-spins and achieve much improved time-to-market of smaller, more robust, more profitable products that exploit the full potential of nanoscale technologies. Teklatech is a privately held company located at Borgergade 20, DK-1300 Copenhagen, Denmark, with commercial and technical representatives in USA, Japan and Europe.
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