Boston, MA, February 6, 2012 – The sixth annual workshop on fully depleted silicon-on-insulator (FD-SOI) technology for advanced semiconductor architectures, featuring technical presentations and discussions among industry peers, will be held on February 24 at the Marriott Marquis Hotel in San Francisco, Calif. This forum, jointly organized by the SOI Industry Consortium, CEA-Leti and Soitec, provides semiconductor IC designers and manufacturers with the latest information and insights on using FD-SOI wafers to produce more power efficient ICs at the performance required for applications in mobile and consumer electronics.
Scheduled for the day after the IEEE International Solid-State Circuits Conference (ISSCC) at the same location, this year’s FD-SOI workshop features presentations by a variety of internationally renowned experts from the semiconductor industry and academia, who also will be available at the event for discussions with attendees. Presentation topics and speakers include:
- Planar Fully Depleted Silicon Technology to Design Competitive SOCs at 28 nm and Beyond: Design Issues by Philippe Flatresse of STMicroelectronics
- Planar Fully Depleted Silicon Technology to Design Competitive SOCs at 28 nm and Beyond: Technology Issues by Michel Haond of STMicroelectronics
- Recent Advances in FD-SOI by Bruce Doris of IBM
- Library and Physical IP Porting for FD-SOI by Jean-Luc Pelloie of ARM
- 20 nm FD-SOI Models by Brian Chen of Accelicon and the SOI Industry Consortium
- FinFET on SOI by Terrence Hook of IBM
- Enabling Substrate Technology for a Large-Volume Fully Depleted Standard by Christophe Maleville of Soitec
- Strain Options for FD-SOI by Olivier Faynot of CEA-Leti
- Advanced FD-SOI Design by Bora Nikolic of the University of California-Berkeley
Planar FD-SOI and SOI-based FinFETs are disruptive technologies, and serious contenders for the next generations of low-power, high-performance architectures. FD-SOI assures an evolutionary path from existing bulk technologies for fabricating next generation low-power, cost-effective CMOS devices for the fast-growing mobile and consumer electronics markets. Fully depleted transistors reach the required circuit speed for data-processing performance while consuming very little power, a critical need in portable devices such as smart phones and tablets.
“Our goal with this workshop is to share the latest product design and processing advances in the FD ecosystem, thereby increasing the semiconductor community’s level of confidence in FD architectures,” said program co-chairman Dr. Horacio Mendez, executive director of the SOI Industry Consortium. “Each year, this event attracts hundreds of industry opinion leaders and key decision makers as SOI applications continue to gain momentum in high-volume markets.”
The workshop is organized by Dr. Mendez, Dr. Olivier Faynot, head of CMOS technology at CEA-Leti, and Dr. Carlos Mazure, chief technology officer of Soitec.
Registration is free by registering at: http://www.soiconsortium.org/workshops/sanfrancisco/
About the SOI Industry Consortium
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing innovation leaders from the entire electronics industry infrastructure, current SOI Industry Consortium members include: AMD, Altera Corp., ARM, Cadence Design Systems, CEA-Léti, FEI, GLOBALFOUNDRIES, IBM, IMEC, Infotech, Kanazawa Institute of Technology, KLA-Tencor, MEMC, Mentor Graphics, MIT Lincoln Laboratories, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain and UMC. Membership is open to all companies and institutions throughout the electronics industry.
For more information, please visit www.soiconsortium.org
