Campbell, CA, May 18, 2011 – Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company, in the post-layout verification market focused on solutions for nanometer design applications, announced today that it is introducing the industry’s first commercial hierarchical 3D extractor, H3D, for post-layout verification. H3D offers hierarchical parasitic extraction, hierarchical netlisting, unlimited capacity, and field-solver accuracy. H3D works with design flows from the leading EDA suppliers.
“Post-layout verification is a major bottleneck in today’s leading edge designs,” said Yuri Feinberg, CEO. “With the introduction of H3D, this bottleneck is removed by providing an accurate extractor that runs with sub-linear performance and delivers a hierarchical output which enables post-layout simulation speed up.
H3D Information
As a hierarchical extractor, H3D is ideally suited for array-based and repetitive design structures, including memories, FPGAs, and image sensors.
Based on Silicon Frontline’s patented technology, H3D’s extraction performance is sub-linear, which ensures as design size grows extraction performance improves. By providing a hierarchical output netlist, post-layout simulation performance becomes sub-linear when using hierarchical simulators.
H3D hierarchical extraction results are design dependent, but have shown performance improvements from 20-120x when compared to flat extraction.
Built on a Hierarchical Random Walk Algorithm, users have the ability to specify the accuracy required on a net by net or block by block basis. H3D provides unlimited capacity due to its hierarchical extraction and parallelization.
The hierarchical output supports R, C, distributed RC and RCCc.
Price and Availability
H3D is shipping early Q3. For pricing information, please contact sales@siliconfrontline.com
About Silicon Frontline’s Products and Guaranteed Accuracy
Silicon Frontline’s post-layout verification software delivers Guaranteed Accuracy, full-chip capacity and performance at least 20 times faster than other commercial field solvers. Users specify the level of accuracy desired, net by net, at the block level or with regular expressions. In this way, the resulting parasitics are guaranteed correct within the specified accuracy range for better design quality.
Silicon Frontline’s software has been used to accurately verify over 300 electronic designs to date. The company’s customers use its software to analyze power devices, improve image sensors, ADCs, flash memories, differential signals and nanometer and Analog Mixed Signal (A/MS) designs. The customer list includes 10 of the world’s top 30 semiconductor companies. In addition, leading foundries have validated Silicon Frontline’s products for use with their nanometer design technologies and reference flows.
F3D (Fast 3D) is used for fast 3D extraction and R3D (Resistive 3D) is used for 3D extraction and analysis of large resistive structures. F3D is chosen for its nanometer and Analog Mixed Signal (A/MS) design verification accuracy, and R3D for analysis that leads to improvements in the reliability and efficiency of semiconductor power devices.
About Silicon Frontline
Silicon Frontline Technology, Inc. provides post-layout verification software that is Guaranteed Accurate and works with existing design flows from major EDA vendors. Using new 3D technology, the company’s software products improve silicon quality for standard and advanced nanometer processes. For more information please visit www.siliconfrontline.com. For sales or general assistance, please email info@SiliconFrontline.com or sft@marubeni-sys.com.
