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Optimized development tool for NXP’s digital signal controller (DSC) architecture:

Lauta (Germany) April 19, 2011 – PLS presents at ESC Silicon Valley Booth 2301 at multicore Expo, the latest Version of the Universal Debug Engine (UDE). UDE 3.0.7 is equipped with optimized test and debug functions for NXP’s LPC4300 highly integrated dual-core system-on-chip (SoC) family and offers unlimited dual-core debugging under a single user interface.

The LPC4300 family brings together an ARM Cortex-M4 with a Cortex-M0 to an asymmetrical dual-core digital signal controller (DSC) architecture. Both processors each operate with their own clock supply and their own power management. However, the communication takes place via a shared memory. 

The JTAG/SWD interface – by which debugging on both cores is possible – is also shared. This requires an intelligent management of the on-chip resources from the debugger. With the UDE 3.0.7, for example, code breakpoints and watchpoints can be set directly in the program window or watch window of the respective Cortex-M. Furthermore, CoreSight diagnostic technologies such as serial wire viewer (SWV), instrumentation trace macrocell (ITM), and data watchpoint and trace (DWT) are extensively supported by the UDE 3.0.7. This guarantees the user a wide range of capabilities. An observation of systems while the application is running is achieved entirely without, or only a very small, change of the timing behavior. The recorded data can be graphically displayed in single form or in linked expressions. A time base for the display can be provided from the target or also from the host PC.

In addition, depending on the type, the new LPC4300 family also provides developers with various peripherals such as USB, CAN, Ethernet, LCD controller, PWM and ADC. These on-chip peripheral modules can be visualized and configured in the debugger at symbolic level in text form. Furthermore, a full Eclipse integration with complete cross debugger functionality is included in the comprehensive test and debug tool UDE 3.0.7.

The JTAG/SWD debug interface of the LPC4300 device is supported by the special JTAG extender of the Universal Access Device family (UAD2+/UAD3+) from PLS and enables a distance of several meters between target and host PC with high immunity against interferences. For LPC4300 developers, this means that the same proven tool is always available for application development, field testing and then later also in customer service. 

PLS Programmierbare Logik & Systeme GmbH

PLS Programierbare Logik & Systeme GmbH, based in Lauta, Germany, was founded in 1990 by Thomas Bauch and Dr. Stefan Weisse. With its innovative modular test and development tools, the company has demonstrated for over two decades its position as an international technology leader in the field of debuggers, emulators and trace solutions for 16-bit and 32-bit microcontrollers. The software architecture of the Universal Debug Engine (UDE) guarantees optimal conditions for debugging SoC-based systems. For example, by means of the intelligent use of modern on-chip debugging and on-chip trace units, valuable functions such as profiling and code coverage are available for the system optimization. Furthermore, the associated Universal Access Device (UAD2/UAD3+) product family, with transfer rates of up to 3.5 MBytes/s and a wide range of interfaces, offers entirely new dimensions for fast and flexible access to multi-core systems. Important architectures such as TriCore, Power Architecture, XC2000/XE166, ARM, Cortex, SH-2A, XScale and C166/ST10 as well as simulation platforms of different vendors are supported. For further information about the company, please visit

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