About IO Checker
IO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins.
IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.
The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour.
What is new in IO Checker 2.0
Version 2.0 adds an FPGA Device View and a TCL command line interface. IO Checker can be used to generate a constraint file from the PCB data (optionally in combination with a toplevel HDL unit). The FPGA constraint file can be updated when inconsistencies have been found between PCB and FPGA data.
Support has been added for the Actel Smart Fusion, Altera Cyclone IV E and Xilinx Spartan 6L, ASpartan 6L, Virtex 6L families. Please check the website for detailed device listings.
Availability and Pricing
IO Checker 2.0 is available now. Prices begin at € 750. IO Checker can be downloaded and evaluated by qualified FPGA and PCB designers.
About HDL Works
HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. HDL Works currently holds EASE, HDL Companion and IO Checker in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.
