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Getting Your Verification Ducks in a Row

Look out! A new way to verify is coming your way. In this week’s Fish Fry, I check out Synopsys’s new Verification IP announcement with a special in-depth interview with Neil Mullinger from Synopsys. Neil and I discuss the details of this new verification platform, what markets it’s destined for, and why whipping up your own verification IP may be a thing of the past. Also this week, I look into a new development in transistor technology headed up by a team at the University of Tel Aviv and why it may or may not involve deli meat. 

I’ve got another MAX V CPLD Development Kit (courtesy of Altera) to give away this week, but you will have to listen to find out how to win.

 

Watch Previous Fish Frys

Fish Fry Links – March 16, 2012

Synopsys Unveils Next-Generation Verification IP for Faster SoC Verification 

More Information about Verification IP from Synopsys

More Information about Protein based transistors

More information about Altera’s MAX V CPLD Development Kit

Email Amelia Dalton

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

John Bruggeman, Former CMO – Cadence Design Systems

Darrin Billerbeck, CEO – Lattice Semiconductor

Lauro Rizzatti, Vice President of Marketing, EVE

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Kapil Shankar, Former CEO – SiliconBlue

Andy Pease, CEO – QuickLogic

Rajeev Madhavan, Former CEO – Magma 

Paul Kocher, President – Cryptography Research Inc.

Anupam Bakshi, CEO – Agnisys


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