fish fry
Subscribe Now

Getting Your Verification Ducks in a Row

Look out! A new way to verify is coming your way. In this week’s Fish Fry, I check out Synopsys’s new Verification IP announcement with a special in-depth interview with Neil Mullinger from Synopsys. Neil and I discuss the details of this new verification platform, what markets it’s destined for, and why whipping up your own verification IP may be a thing of the past. Also this week, I look into a new development in transistor technology headed up by a team at the University of Tel Aviv and why it may or may not involve deli meat. 

I’ve got another MAX V CPLD Development Kit (courtesy of Altera) to give away this week, but you will have to listen to find out how to win.

 

Watch Previous Fish Frys

Fish Fry Links – March 16, 2012

Synopsys Unveils Next-Generation Verification IP for Faster SoC Verification 

More Information about Verification IP from Synopsys

More Information about Protein based transistors

More information about Altera’s MAX V CPLD Development Kit

Email Amelia Dalton

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

John Bruggeman, Former CMO – Cadence Design Systems

Darrin Billerbeck, CEO – Lattice Semiconductor

Lauro Rizzatti, Vice President of Marketing, EVE

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Kapil Shankar, Former CEO – SiliconBlue

Andy Pease, CEO – QuickLogic

Rajeev Madhavan, Former CEO – Magma 

Paul Kocher, President – Cryptography Research Inc.

Anupam Bakshi, CEO – Agnisys


Leave a Reply

featured blogs
Mar 3, 2021
In grade school, we had timed math quizzes. With a sheet full of problems and the timer set, the goal was to answer as many as possible. The key to speed is TONS of practice and, honestly, memorization '€“ knowing the problems so well that the answer comes to mind at first ...
Mar 3, 2021
The recent 34th International Conference on VLSI Design , also known as VLSID , was a virtual event, of course. But it is India-based and the conference ran on India time. The theme for this year was... [[ Click on the title to access the full blog on the Cadence Community s...
Feb 26, 2021
OMG! Three 32-bit processor cores each running at 300 MHz, each with its own floating-point unit (FPU), and each with more memory than you than throw a stick at!...
Feb 25, 2021
Learn how ASIL-certified EDA tools help automotive designers create safe, secure, and reliable Advanced Driver Assistance Systems (ADAS) for smart vehicles. The post Upping the Safety Game Plan for Automotive SoCs appeared first on From Silicon To Software....

featured paper

Authenticating Remote Automotive Peripherals Using GMSL Tunneling

Sponsored by Maxim Integrated

Authentication can be applied to automotive environments to protect peripheral components from third-party counterfeits. This application note details how to implement automotive authentication with the use of gigabit multimedia serial link (GMSL).

Click here to download the whitepaper

Featured Chalk Talk

Benefits of FPGAs & eFPGA IP in Futureproofing Compute Acceleration

Sponsored by Achronix

In the quest to accelerate and optimize today’s computing challenges such as AI inference, our system designs have to be flexible above all else. At the confluence of speed and flexibility are today’s new FPGAs and e-FPGA IP. In this episode of Chalk Talk, Amelia Dalton chats with Mike Fitton from Achronix about how to design systems to be both fast and future-proof using FPGA and e-FPGA technology.

Click here for more information about the Achronix Speedster7 FPGAs