chalk talk
Subscribe Now

Moving Between FPGA and ASIC with High-Level Synthesis


Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible.
But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow.

Click here for more information about Catapult® High-Level Synthesis

Leave a Reply

featured blogs
Dec 18, 2018
Building on their existing partnership, Avnet, a leading global technology solutions provider, and Samtec, today announced an extension of their distribution agreement. Avnet customers in Asia Pacific and Japan now have access to Samtec'€™s full product portfolio....
Dec 18, 2018
A couple of weeks ago, the cover story of The Economist was Chip Wars: China, America and silicon supremacy . For the last few years it has been the biggest story in the semiconductor industry. You... [[ Click on the title to access the full blog on the Cadence Community sit...
Dec 12, 2018
The possibilities for IoT devices, much like the internet itself, are endless. But with all of those possibilities comes risks....
Nov 14, 2018
  People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...