Getting RTL right for your chip design is a difficult engineering and verification challenge with very high stakes. And, most of us use a variety of tools – including spreadsheets and text documents – to capture our design intent and details. In this episode of Chalk Talk, Amelia Dalton chats with Anupam Bakshi from Agnisys about some great solutions for getting from design specifications into verified RTL.
Click here for more information about IDesignSpec.
Click here to evaluate a full version of IDesignSpec.
Click here for more information about ARV.
Click here to evaluate a full version of ARV.
Name : Anupam Bakshi
Designation :CEO, Agnisys Inc.
Twitter : @bakshia
