Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.
Click the link below to download a free whitepaper entitled “Hierarchical Timing Analysis: Pros, Cons, and a New Approach.”
Click the link below for more information about Cadence’s Tempus Timing Signoff Solution.