Allan Cantle knows what it takes to design high-performance digital systems. He’s been proving it since his early days at BAE Systems, where he was creating real-time simulations of evasive enemy targets to be used with real-world missiles in targeting practice. Allan has always had a knack for decomposing a complex problem into manageable-sized chunks, then mapping those chunks onto the appropriate architectures with the right interconnect to hit aggressive performance goals in the most economical way. Allan has a passion for working on complicated computing problems and isn’t afraid of trying varied technologies to … Read More → "Allan Cantle"

Introduction

FPGA logic design no longer rules the project schedule like it once did. Twenty years ago, implementing the logic in 20 and 24-pin programmable logic devices, such as 22V10s or PAL16R8s, was tricky, given the state of programmable logic tools at the time, but doing so certainly didn’t consume the lion’s share of the overall design effort. Back then, the deciding factor in project schedules was typically the design of the PCB onto which those devices were placed. As the sophistication of programmable devices has increased – evolving … Read More → "It’s Not All About the FPGA Anymore"

It’s difficult for a technical conference to get just the right balance. Too much tradeshow, not enough industry participation; too many irrelevant sessions, too many times over the same topic; not enough attendees, too many attendees… it’s like trying to hit your design constraints for power, cost, area, performance, and reliability all at the same time, while still meeting your schedule. You struggle to reach one goal only to find out that you’ve slipped behind on the others. It’s a fight to find a creative solution that will converge.

Interest in FPGA reliability is not restricted to SEU environments. The US critical infrastructure, for example, often demands 24/7 operations and thus hi-reliability is frequently sought and very few, if any, of the infrastructure components are in SEU environments.

System failures are largely attributed to software-level errors such as unexpected input values, timing violations, and I/O shortfalls. To decrease the probability of system failure, many specialized, checking functions can be performed during runtime to make the software error-resilient. However, system performance suffers because the checking functions consume processor cycles that would otherwise be used for the mission … Read More → "Migrating FPGA Virtual Gates to MROM Reduces Reliability Risk"

High-reliability design considerations are fast becoming an art that system engineers have to undertake very early on in the design process, often beginning with a designer’s choice of system silicon. For designers seeking flexibility and time-to-market advantages, high-reliability FPGAs are a good choice. However, not all high-reliability designs are created equal. There is a broad spectrum of high-reliability designs out there today, from space-bound satellites to anti-lock braking systems in our ground-based vehicles. While there are obvious similarities between these two types of systems, there are also some key differences, all of which become important … Read More → "FPGA Reliability in Space-Flight and Automotive Applications"

Most of us know Moore’s law to have only one independent variable – time. Mr. Moore predicts that, as time goes by, the complexity of our electronic designs increases exponentially. One thing Mr. Moore never mentioned in public, however, is the secret second factor. Aerospace engineers have long been aware that Moore’s law has a little- known term in the denominator. This factor is something like “one plus altitude squared.” As your design gets farther from the ground, the fabrication technology goes back in time along the line of progress. Until recently, by … Read More → "Space Silicon"

The TCP/IP protocol suite is the de facto worldwide standard for communications over the Internet and almost all intranets. Interconnecting embedded devices is becoming standard practice even in device classes that were previously stand-alone entities. By its very definition, an embedded architecture has constrained resources, which is often at odds with rising application requirements.

Achieving wire-speed TCP/IP performance continues to be a significant engineering challenge, even for high-powered Intel™ Pentium™-class PCs. In this article, we’ll discuss the per-byte and per-packet overheads limiting TCP/IP performance and present the … Read More → "Considerations for High-Bandwidth TCP/IP PowerPC Applications"

When I was a kid, my Dad had a big’ol vacuum-tube audio amplifier. It was massive, heated the room, and took several minutes to “warm up” before it was ready for duty. Sometimes the transformers would hum along with the music, which was OK if the tune was in a key that was a multiple of 60Hz. To me, the thing seemed a bit clunky compared with the transistor-based mainstays of the day. When I asked Dad about the amp, he’d always reply “Well, son, they used to make them all that … Read More → "Crossing Over"

Myopia is one of the few unfortunate consequences of specialization. While focus, refinement, and evolution deliver us some of our most impressive efficiencies, indiscriminate rule breaking is more often the root of spectacular progress. We walk along in our well-walled worlds day-to-day, carefully categorizing concepts like “Field Programmable Gate Array,” “Structured and Platform ASIC,” and “Programmable System on Chip,” and we forget to color outside the lines occasionally, just to see what happens.

Actel announced its new Fusion architecture this week, and somebody clearly went a little crazy with the coloring … Read More → "Actel Adds Analog"

Back when FPGAs were simpler devices, in-system debug was sufficient. Turning a re-spin in response to a specification violation found on the bench was a quick and easy process. Life was great, since re-spins were essentially “free”. This is no longer the case today. One company recently spent three entire months trying to incorporate just one late-coming specification change, because the design team encountered difficulties meeting requirements after making that single change. This is not an isolated case; increasingly painful re-spins are no longer a rare occurrence. Clearly, this particular re-spin cost the customer dearly. … Read More → "A New Spin on FPGA Re-spins"