Articles – Page 545

April 8, 2008

About a decade ago, FPGA design followed in the footsteps of ASIC and went language-based. For a very long time, the only question we asked ourselves was “VHDL or Verilog?” It was reminiscent of the “Paper or Plastic?” scenario in the grocery checkout line. Gradually, however, people sneaked into the FPGA-designing fold that weren’t FPGA designers. Who are these folks anyway? We’ve got DSP engineers, embedded systems designers, board designers, supercomputing folks… the list goes on and on.

Apparently all those new … Read More → "One to Many"

Java Earning Its Wings

Aonix Makes Real Time Almost Safety Critical

by Bryon Moyer

April 8, 2008

It happened just like that. In the middle of a conversation, he got a kind of misty look in his eyes, like something wasn’t quite right. His breathing became more labored, he hunched forward a bit, and the next thing you knew, he was in full heart attack mode. An ambulance was quickly called for; this is where seconds count. As the ambulance was en route, efforts were made to clear the way for the EMTs so that they could get to work as quickly as possible. The main door was propped open, and an … Read More → "Java Earning Its Wings"

Attacking Abuses of Power

Part 2

by Bryon Moyer

April 1, 2008

A few weeks ago, we started looking at ways of reducing power consumption when designing SoCs. We divided the world into the front-end, where the big payoff is, and the back-end, with useful techniques that have less dramatic impact. We looked at architecture and system design, hardware/software allocation and C-to-RTL, multicore, Multi-Voltage Supply (MVS), power switching, Dynamic Voltage/Frequency Scaling (DVFS), and Adaptive Voltage Scaling (AVS). These are techniques that can give power savings in the range of 30-50%. Having addressed those, there are numerous back-end techniques that can give more modest, but nonetheless valuable, power savings. We& … Read More → "Attacking Abuses of Power"

Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations

by Bryon Moyer

April 1, 2008

Related Applications

None

Field of the Invention

Way out in left field.

Background of the Invention

For purposes of gathering together for reasons including but not limited to sharing information, making commercial announcements, receiving training, professional networking, escaping a nagging spouse or children, and racking up frequent flier miles, it is common for engineering professionals to attend conferences or conventions. Such conferences may consist of convention-center catered meals, speeches in which very important people say what everyone already knows, an exhibit hall wherein more women … Read More → "Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations"

Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations

by Bryon Moyer

April 1, 2008

Related Applications

None

Field of the Invention

Way out in left field.

Background of the Invention

For purposes of gathering together for reasons including but not limited to sharing information, making commercial announcements, receiving training, professional networking, escaping a nagging spouse or children, and racking up frequent flier miles, it is common for engineering professionals to attend conferences or conventions. Such conferences may consist of convention-center catered meals, speeches in which very important people say what everyone already knows, an exhibit … Read More → "Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations"

Tools and Transceivers

Dual Xilinx Announcements

by Kevin Morris

April 1, 2008

In the old days, we had only two kinds of FPGA – small and smaller, also known as slow and slower, or hot and hotter… The technology was useful for a few high-value applications, but it was limited on all three fronts – density (cost), speed, and power — from attacking a much broader market. As we waltzed along the to the three-count meter of Moore’s Law, all three critical parameters improved. Density went up, frequency got faster, power cooled down, and people got happier.

After a few rounds, however, FPGAs had pretty … Read More → "Tools and Transceivers"

As Easy As Pie

by Bryon Moyer

April 1, 2008

ANNOUNCER: It’s spring, the harvest is and holidays are behind us, and the apples in cold storage are starting to age. Someone needs to come to their rescue before it’s too late. And that can mean only one thing here in Kitchen Stadium: it’s Time for Pie. So today’s challenge will be an homage to Mom’s apple pie.

But things are going to work a little differently this time out. Instead of a challenger taking on one of the Iron Chefs, five Iron … Read More → "As Easy As Pie"

MIPS Moves on Multi-Core

MIPS32 1004K

by Kevin Morris

April 1, 2008

At first, the concept of “multi-core” from a processor IP company might seem a bit confusing. Couldn’t we already put multiple MIPS cores on our devices? If your concept of multi-core ends with putting more than one processor on a chip, you may not be yet dialed into the subtleties.

This week, MIPS launched their highest-performance solution ever with the new MIPS32 1004K “Coherent Processing System” – a multi-core, multi-threaded IP solution. The challenge of keeping all your cores busy in a symmetric multi-processing (SMP) system is actually … Read More → "MIPS Moves on Multi-Core"

Bigger and Better Storage

by Bryon Moyer

March 25, 2008

Last week’s ISSCC and DesignCon conferences included presentations of developments in non-volatile memory, and we present some highlights here. Some of the papers discussed developments in novel cell types; others addressed improvements in more well-adopted technologies. So first let’s review the different kinds of non-volatile cells being covered to set some context.

The lives of a cell

Flash is the best known of the technologies; it’s the one that the least technically savvy of us might actually go out and buy … Read More → "Bigger and Better Storage"

ISSCC Processor Fest

by Bryon Moyer

March 25, 2008

There are some places it seems everyone wants to be. The Oscars. An inaugural ball. Mardi Gras. New Years in Times Square. (OK, pre-War on Terror.) Well there was a new member of this list a while back that might not have sprung to mind immediately: the microprocessor session at ISSCC, packed to the gills. Four new processors were presented, plus one process migration to 45 nm. The bragging rights on such chips are typically all about performance (or performance efficiency), and everyone fusses over clock rates and bus sizes and various and sundry other numbers, but, in … Read More → "ISSCC Processor Fest"