Taming Variability
Back in the dark ages, when I first moved into the semiconductor realm, I used to compare the process geometries with the thickness of a human hair – which caused gasps of disbelief in a lay audience. Holding up a four-inch wafer of 16K SRAMS alongside a transistor can with its three wires, then explaining the many hundreds of thousands of can equivalents that were contained in the wafer, usually also caused gasps.
At a recent presentation I heard Kelin Kuhn, an Intel Fellow and a dynamic speaker, explain that a 32nm memory cell was dwarfed by … Read More → "Taming Variability"

