Free software enables development of IEEE 1149.1-2011 JTAG and P1687/IJTAG based Infrastructure IP for FPGA and SoCs
Dover, NH –Marketwire – November 3rd, 2010 — Intellitech announced today a free version of its NEBULA software to enable FPGA and SoC designers to develop and validate JTAG/IJTAG based infrastructure IP. The software is targeted for designers who want to validate internal JTAG accessible IP blocks and instruments using the PDL language of upcoming 1149.1-2011 and future IEEE P1687. PDL – Procedure Definition Language is common to both standards and enables developers to describe the operation of the JTAG accessible IP. End customers and integrators can then re-use the PDL provided without re-targeting when the IP … Read More → "Free software enables development of IEEE 1149.1-2011 JTAG and P1687/IJTAG based Infrastructure IP for FPGA and SoCs"

