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Free software enables development of IEEE 1149.1-2011 JTAG and P1687/IJTAG based Infrastructure IP for FPGA and SoCs

Dover, NH –Marketwire – November 3rd, 2010 — Intellitech announced today a free version of its NEBULA software to enable FPGA and SoC designers to develop and validate JTAG/IJTAG based infrastructure IP. The software is targeted for designers who want to validate internal JTAG accessible IP blocks and instruments using the PDL language of upcoming 1149.1-2011 and future IEEE P1687. PDL – Procedure Definition Language is common to both standards and enables developers to describe the operation of the JTAG accessible IP. End customers and integrators can then re-use the PDL provided without re-targeting when the IP … Read More → "Free software enables development of IEEE 1149.1-2011 JTAG and P1687/IJTAG based Infrastructure IP for FPGA and SoCs"

You Got Your Peanut Butter on My Fabric

You probably remember the TV commercials.  Two strangers randomly collide – co-mingling their confections in a fictitious fortuitous coincidence – giving the world the magic that is Reese’s Peanut Butter Cups.  It’s a lie, but fact emerges from farce – chocolate and peanut butter make a very nice combination.

FPGA fabric and optimized circuit blocks make a very nice combination, too.  Why settle for lower performance, lower density, and higher power consumption for the parts of your circuit that do not require the flexibility of FPGA fabric?  Why … Read More → "You Got Your Peanut Butter on My Fabric"

Achronix To Build The World’s Most Advanced Field Programmable Gate Arrays (FPGAs) On Intel 22nm Process Technology

San Jose, Calif. — Achronix Semiconductor Corp. today announced strategic accessto Intel Corporation’s 22 nanometer (nm) process technology, and plans to developthe most advanced Field Programmable Gate Arrays (FPGAs).

The Achronix Speedster22i FPGA family will shatter existing limitations of FPGAs,allowing cost effective production of high performance devices over 2.5M LUTs insize, equivalent to an ASIC of over 20 million gates.

Taking advantage of the performance and power savings of Intel’s 22nm processtechnology, Speedster22i will also extend the boundaries of FPGA speed and powerefficiency, enabling as much as 300% higher performance, 50% lower … Read More → "Achronix To Build The World’s Most Advanced Field Programmable Gate Arrays (FPGAs) On Intel 22nm Process Technology"

Green Hills Software to Present and Exhibit at the ARM Technology Conference 2010

SANTA BARBARA, CA — November 2, 2010 — Green Hills Software, Inc., the largest independent vendor of embedded software solutions, will deliver technology presentations at the ARM Technology Conference in Santa Clara, CA, during the week of November 8, 2010. At booth #307, Green Hills Software will also demonstrate its latest embedded software solutions.

Green Hills Software speakers will present in the Santa Clara Convention Center:

Topic: Tips and Tricks for Debugging
When: Wednesday, November 10, 2010   3:30pm — 4:20pm
Where: Room 207, Track: Software Debugging Tools and Techniques
Who: Greg Davis, Director of Engineering, Compilers, Green Hills Software</ … Read More → "Green Hills Software to Present and Exhibit at the ARM Technology Conference 2010"

Conexant and Grain Media Deliver Design Solution for High-Density Video Surveillance Applications

NEWPORT BEACH, Calif.–(BUSINESS WIRE)– Conexant Systems, Inc. (NASDAQ: CNXT), a leading supplier of innovative semiconductor solutions for imaging, audio, embedded modem, and video surveillance applications, and Taiwan-based Grain Media, a leading system-on-chip (SoC) design company for video, image processing, and surveillance applications, today announced the availability of a complete hardware and software reference design for 16-channel digital video recorders (DVRs) used in security and surveillance applications. The new reference design is based on Conexant’s multichannel video decoders and Grain Media’s advanced H.264 compression SoC solution.</ … Read More → "Conexant and Grain Media Deliver Design Solution for High-Density Video Surveillance Applications"

2MHz, DC Accurate Synchronous Step-Down DC/DC Controller with Differential Output Sensing & Clock Synchronization

MILPITAS, CA – November 2, 2010 – Linear Technology Corporation introduces the LTC3833, a high frequency controlled on-time synchronous step-down DC/DC controller with differential output voltage sensing and clock synchronization. The controlled on-time, valley current-mode architecture forces a very fast transient response by increasing its operating frequency during a transient event, allowing the LTC3833 to recover from a large load step in only … Read More → "2MHz, DC Accurate Synchronous Step-Down DC/DC Controller with Differential Output Sensing & Clock Synchronization"

Synopsys’ New DesignWare STAR ECC IP Helps Reduce Embedded Memory Transient Errors

MOUNTAIN VIEW, Calif., Nov. 2, 2010 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of the DesignWare® STAR ECC (Self-Test and Repair Error Correcting Codes) IP as a part of its DesignWare STAR Memory System® product family. The new DesignWare STAR ECC IP offers a highly automated design implementation … Read More → "Synopsys’ New DesignWare STAR ECC IP Helps Reduce Embedded Memory Transient Errors"

Achronix (name)Drops the Big One

Until this week, the highest-density FPGAs announced in the world – fabricated on the smallest process geometry – were made by exactly the company you’d expect.

That’s right, TSMC.

Oh, you thought I was going to say “Xilinx and Altera.” Fair enough.  Certainly FPGAs are created by a collaboration between the FPGA vendor – a “fabless” semiconductor company like Xilinx or Altera, and a semiconductor fab – like TSMC or UMC.  The semiconductor fab provides the process technology and the manufacturing, and the … Read More → "Achronix (name)Drops the Big One"

Moving Back In Time

It sounds like old times, something that’s been done before.

You take a bit of extra logic, tap into your JTAG infrastructure (pun intended), add some IP, and look into what’s happening with your FPGA. And you’d say, “Oh, that sounds like Altera’s SignalTap or Xilinx’s ChipScope.”

OK, so then say you add some logic to your ASIC, capture and compress a bunch of data, and decompress it on the way out. And you’d say, hey, that sounds sort of like … Read More → "Moving Back In Time"

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