feature article
Subscribe Now

Xilinx 1, Intel 0

Big X Scores First in the New Rivalry

I’ll just say right up front that this is really mostly about bragging rights. No corporate destinies are shaped, no fortunes won or lost, no pivotal temporal butterflies crushed by the fact of who ships a new FPGA generation first. But, with the same fuzzy logic that drives reality shows, football matches, and political polls, those in the FPGA business put a lot of energy into the unofficial biennial Moore’s Law derby to see who can ship the first FPGAs on a new process node.

This time, the stakes were higher than ever. 16/14nm is the first node where both big FPGA companies are shipping FinFET-based devices (Achronix scooped them both, however, by shipping FinFETs with their 22nm Intel-fabbed devices over a year ago). Plus, this is the first round that pitted the Xilinx/TSMC duo against the newly formed Altera/Intel team https://www.eejournal.com/blog/altera-partners-with-intel-for-14nm-tri-gate-fpgas4/. Lots of experts were betting on Intel. After all, Intel is widely viewed as having an overall lead in fabrication technology, and the company had already shipped a generation of FinFET-based chips (Intel calls them Tri-Gate) at 22nm. 

Altera announced their 14nm plans almost three years ago. Altera’s “Generation 10” announcement was June 2013. Xilinx waited another 20 months before unveiling their Ultrascale+ roadmap in February 2015. 20 months is an eternity in what we at EE Journal refer to as “Moore’s Law Chicken”. Did the long delay indicate that Xilinx was lagging behind with TSMC? Or, had they just gotten so cocky they didn’t feel the need to answer Altera’s taunt?

Then, to add fuel to the fire, Intel announced plans to acquire Altera right in the middle of the scuffle. Yep, the FPGA biz is exciting, folks. Grab yourself some popcorn. We’ll sell you the whole seat, but you’ll only need the edge!

Well, the first points have now been posted to the scoreboard. Xilinx now claims to be shipping both their Zynq Ultrascale+ MPSoCs and, most recently, their Virtex Ultrascale+ devices. The company claims to have engaged with over 100 customers on Ultrascale+ and to have already shipped devices and/or boards to over 60 of these customers. This is a happy contrast with the past “norm” in the FPGA industry, where “now shipping” used to mean one AE was put on a plane with a briefcase containing the one working part in existence, headed to a key customer site solely so the vendor could claim to have “shipped.”

Clearly, Xilinx is gloating a little here.

As far as we know, Altera oops I mean Intel has not yet taped out their Stratix 10 family based on Intel’s 14nm Tri-Gate process technology. Is shipping first all about bravado, or are there real business benefits as well? In some markets, it seems there are probably significant rewards for shipping first. Take, for example, the highly specialized market for FPGA-based prototyping and emulation. There are only a few companies in the world who produce FPGA prototyping systems and FPGA-based emulators. Their requirements for FPGAs are among the most straightforward in the business. “Give us as many LUTs as you can possibly pack onto a chip.”  There’s an enormous advantage to whatever prototyping/emulation company can ship hardware with the biggest FPGAs, so whichever vendor can deliver the next 2x advantage tends to win almost all the business. Once the prototypers have released new boards, they’re not in the market for FPGAs again until the next time the size doubles.

Xilinx cleverly captured that flag months ago by shipping their largest devices designed specifically for the emulation and prototyping market based on TSMCs 20nm process. This allowed them to grab most of the available sockets that were looking for 4-million-LUT devices long before Altera will be able to deliver their similar-sized parts. Altera skipped the 20nm node with their Stratix devices, choosing instead to put their energy into the 14nm effort.

In most application areas, however, there’s a lot more wiggle room in the adoption of the latest FinFET-based FPGAs. The real win with FinFETs (on top of the usual gains from yet another process shrink) is reduced power consumption and better performance-per-watt. In many markets, power consumption is becoming the key driver, so upgrading systems with more efficient chips is a major win for customers.

Ultrascale+ brings a lot of new capabilities for Xilinx beyond performance-per-watt, however. The company has upgraded transceivers with up to 28 Gbps backplane performance and up to 32.75 Gbps chip-to-chip performance. For FPGA companies, transceiver design is critical. History is littered with situations where launch of a new FPGA family was delayed or severely impacted by the challenge of delivering transceivers on a new process. In fact, and we’re speculating here, we wouldn’t be surprised if transceivers didn’t account for the relative delays in Altera’s shipping Stratix 10.

One thing today’s high-end applications can never seem to get enough of is high-speed memory. With the new generation of devices, Xilinx has attacked the memory glut on several fronts. DDR4 at 2666 Mbps improved block RAM and a new concept called UltraRAM that provides massive amounts of fast, on-chip storage. 

Xilinx has also beefed up their built-in standard interfaces with 100G EMAC, 150G Interlaken, PCI Express Gen3 x16, and Gen4 x8, and with Ultrascale+ MIPI D-PHY support for talking to those newfangled mobile interfaces.

As we mentioned, one of the big benefits of FinFETS is performance-per-watt. This is because the increased gate surface area offers lower leakage and lower operating voltage while delivering faster switching speeds. This raises a question, though: What do you want to do with this new super power? With Ultrascale+, Xilinx gives you a couple of different options (.85v and .72v) for core voltage. In the one case, you get more speed at a similar power, and in the other case, you get a similar speed with much less power. So, if your design already has the performance it requires on a previous generation device, you can dial back the core voltage for some significant power savings. Or, if you need to go faster than you’ve ever gone before, you can get that additional speed and still probably end up saving a little bit of power.

It’ll be interesting to see some of the amazing applications that are enabled by this next generation of programmable logic technology. The functionality, performance, and efficiency of these devices are unlike anything the industry has ever seen. Whether that improvement manifests itself in remarkable new-end products is now up to you.

12 thoughts on “Xilinx 1, Intel 0”

  1. I’ll just point out that TSMC 16nm is really just 20nm with a finfet. I’ll also point out that the latest part from Xilinx is just a little bigger than their last part. Altera did a big change in the architecture of the Stratix 10. For example single precision floating point and the millions of registers in the wires (I call them synchronous wires). The configuration mechanisms are all new and as Altera (now Intel) has been saying “architecture matters”. I was so disappointed that Xilinx didn’t do floating point in hardware. How are they going to compete in the data center? Finally Xilinx is not going to a real 14nm device and are going to wait out that node with their fake 16nm until 10nm comes out. That’s going to be a long time. What I see now is Xilinx taking the easy path waiting to be bought.

  2. Pingback: www.cpns2016.com
  3. Pingback: DMPK Services
  4. Pingback: zdporn.com
  5. Pingback: agen poker

Leave a Reply

featured blogs
Jun 6, 2023
Learn about our PVT Monitor IP, a key component of our SLM chip monitoring solutions, which successfully taped out on TSMC's N5 and N3E processes. The post Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes appeared first on New Horizons for Chip Design....
Jun 6, 2023
At this year's DesignCon, Meta held a session on '˜PowerTree-Based PDN Analysis, Correlation, and Signoff for MR/AR Systems.' Presented by Kundan Chand and Grace Yu from Meta, they talked about power integrity (PI) analysis using Sigrity Aurora and Power Integrity tools such...
Jun 2, 2023
I just heard something that really gave me pause for thought -- the fact that everyone experiences two forms of death (given a choice, I'd rather not experience even one)....

featured video

Automatically Generate, Budget and Optimize UPF with Synopsys Verdi UPF Architect

Sponsored by Synopsys

Learn to translate a high-level power intent from CSV to a consumable UPF across a typical ASIC design flow using Verdi UPF Architect. Power Architect can focus on the efficiency of the Power Intent instead of worrying about Syntax & UPF Semantics.

Learn more about Synopsys’ Energy-Efficient SoCs Solutions

featured paper

EC Solver Tech Brief

Sponsored by Cadence Design Systems

The Cadence® Celsius™ EC Solver supports electronics system designers in managing the most challenging thermal/electronic cooling problems quickly and accurately. By utilizing a powerful computational engine and meshing technology, designers can model and analyze the fluid flow and heat transfer of even the most complex electronic system and ensure the electronic cooling system is reliable.

Click to read more

featured chalk talk

NXP GoldVIP: Integration Platform for Intelligent Connected Vehicles
Today’s intelligent connected vehicle designs are smarter and safer than ever before and this has a lot to do with a rapidly increasing technological convergence of sensors, machine learning, over the air updates, in-vehicle high bandwidth networking and more. In this episode of Chalk Talk, Amelia Dalton chats with Brian Carlson from NXP about NXP’s new GoldVIP Platform. They examine the benefits that this kind of software integration platform can bring to automotive designs and how you can take a test drive of the GoldVIP for yourself.
Nov 29, 2022