feature article
Subscribe Now

Selling Your Brain

Patent Law is a Slippery Slope for Engineers

Patent Law was created to protect and encourage inventors. The original intent is noble: when you invent something, the patent system is designed to give you a period of exclusivity where you can profit from your work and creativity without fear of someone copying your idea without compensating you.

However, the patent system didn’t contemplate the reality of today’s professional engineering environment, where the majority of engineers are employed in a work-for-hire situation by large corporations, and where those engineers frequently move from one large corporation to another. In that situation, our patent system breaks down badly.

When you go to work for a large company, you typically sign an employment agreement. Buried in the sea of legalese is a section where you give up the rights to anything you invent while in the employ of that company. You are selling your future inventions in return for the stability of a regular paycheck. The company will combine your work and inventions with the work and inventions of other engineers, and it will own the rights to the resulting technology. You will get a regular paycheck, benefits, and a cubicle – and the use of some spiffy lab equipment. 

Many engineers also make the incorrect assumption that they are selling out for a measure of employment stability, but the reality of public corporations today has caused the concept of long-term employment to fade into obscurity like a bad joke – a bit of kitsch from a forgotten era that never really existed – where the milkman delivers your dairy supply to your doorstep each week and the postal carrier waves cheerfully over your white picket fence as he drops off the mail – and you grab your briefcase, slip on your gold watch commemorating 25 years of loyal service, and cruise off to the office, where you’ll mingle with your lifelong colleagues – almost like a second family. 

In today’s cutthroat corporate culture, however, corporations come and go. Businesses are bought and sold with such regularity that many engineers can end up working for five or six different companies without ever changing jobs. Layoffs in technology companies are de rigeur, and recruiting practices center around collecting commissions for stealing the best talent from competitors. The result is that tenure is almost an obsolete concept, and engineers must have the same adaptability in constantly changing employment as they do in keeping up with rapidly evolving technology.

This brings us to the crux of the matter. There is a fuzzy line – much fuzzier than anyone wants to admit – between what you have invented and your expertise. Most of us who have invented things have had this feeling, like your invention is a part of your engineering soul, like it is hard to distinguish between the thing you have invented and the thing you are. An invention is seldom a single atomic thing. It is more often a journey – a collection of small discoveries that fortuitously fit together to create something larger: a solution to a problem. It is a squadron of ideas and expertise flying in formation toward some mutually agreed-upon destination. 

As our careers advance, those ideas become a part of the fabric of our expertise. When we encounter a particular situation, we apply the methods we have learned and invented almost without thinking. We make new solutions to problems based on our accumulated expertise and experience. That’s what they pay us for. Without that, all engineers would be paid as fresh college graduates, and experience would have no value.

When the corporate patent team comes knocking at the office door, most engineers are flattered. We see the arrival of the legal troops as validation – as a sign that the work we are doing is strategically important to the company. We envision our names engraved on a little placard on the company fame wall, our genius immortalized there with the best of the best in our company.

Then, we face the torture of the claims. We must simplify and generalize our invention. We must distill it down to a level where an intelligent but non-technical reader could make sense of it. Where a member of a jury “of our peers” would have a hope of determining whether some other solution did or did not infringe on our work. It requires us to make something out of our invention that it is not – a set of fences around a specific set of interlocking ideas in our brains. It is sometimes a bit sad to see the ownership of our ideas go off to another entity, but this is the deal we made – and our employer is like our family, our caretaker… until it isn’t.

When that day comes and we move to a different company, we must have a professional lobotomy. We are supposed to identify, extract, and surgically isolate those ideas in our brains that are now the legal property of our former employers from the larger collective expertise that we have developed and accumulated during our careers. The new company is hiring us for our expertise, but some of that expertise is now taboo. Our engineering knowledge is like swiss cheese, with legal holes scooped out by the ghosts of patents past.

A couple of weeks ago, I was writing the article on Altera’s amazing new Stratix 10 FPGAs with HyperFlex technology. HyperFlex is an important architectural innovation. It allows FPGA logic to execute much faster by giving the implementation software flexibility in the location of the registers. This flexibility allows the movement of delay from one clock cycle to another – borrowing positive slack from one place to eliminate negative slack in another. It bends the rigid rules of synchronous design by introducing a tiny bit of asynchronicity in order to make timing closure easier and more deterministic. It accomplishes this by including a giant string of tiny registers called Hyper-Registers in every routing path.

Something in this story rang familiar.

Two things came to mind – the “picoPIPE” technology developed by Achronix and used in their original FPGAs. In picoPIPE, a plethora of registers allowed arbitrary synchronization points instead of rigid register boundaries – enough that Achronix quietly called theirs “asynchronous FPGAs.” Achronix subsequently backed off on the picoPIPE idea in favor of the more traditional FPGA architecture they sell today.

The second thing that came to mind was Tabula’s “Spacetime” FPGAs. I previously wrote about a method they used to ensure timing closure with “time vias,” which were strings of transparent latches inserted into the routing that allowed retiming of logic. A bit of research revealed that Tabula has a patent – 9,041,430, Jan 28, 2014 that covers this technique: 

Operational time extension

Jan 28, 2014 – TABULA, INC.

An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently. 

Tabula, a spectacularly innovative company, ceased operations earlier this year. Their engineers have all gone off to pursue other opportunities. In fact, further research showed that a number of former key Tabula technologists are now working at Altera.

I was unable to find the current status of Tabula’s patent portfolio. Normally, in situations where a technology startup is liquidated, the patent portfolio is auctioned off. We do not know whether such an auction has taken place, or who currently owns Tabula’s patents, but it appears on the surface that whoever does own the patents could wreak havoc on Altera – locking their most important new product family up in litigation, right at a time when the company is in the middle of a sixteen-billion-dollar acquisition by Intel.

Did Tabula’s technologists go to work at Altera and then re-create Tabula’s patented technology in Stratix 10? That would be a major failure of the engineering job-change lobotomy we described above. We contacted Altera to find out. Altera replied: “We are aware of Tabula and we are confident that we don’t have a conflict with the S10 implementation.”

Altera’s response is interesting. I have now read the Tabula patent in its entirety, and it is very well written and the claims are nicely broad. I have a EE degree, over thirty years of experience, and I’m an expert in this specific area of technology. If I were at Altera, and I knew someone else held this patent, I’d be terrified. What does Altera know that we don’t?

Perhaps Altera’s experts have done a similar analysis and, with benefit of more details about Altera’s implementation of HyperFlex, have reached the opposite conclusion and decided that HyperFlex does not infringe Tabula’s patent. Or, perhaps Altera has quietly bought or licensed the patented technology from Tabula. Or, maybe Altera is just putting on a confident face for the press while they scamper to do damage control. My bet is on option 2  – that Altera has licensed the technology or bought the patent and we just haven’t heard about it yet.

There are a few other considerations that make this even more interesting. Achronix has patents that pre-date the Tabula ones, which could (in my opinion) well throw a big wrench into any of these scenarios. And, there are also pretty credible rumors that Xilinx is now developing similar technology that is as yet unannounced. This whole thing could end up in a big legal mess. Let’s hope it doesn’t prevent the world from having access to this useful and interesting technology.

Clearly, something needs to be done to improve the patent system and our handling of intellectual property in general. Perhaps patents should remain in the hands of their inventors – moving with them from company to company in the same way that professional sports stars carry their talents from team to team. We might then see a class of “superstar” engineers guarded jealously by their employers. Of course that solution, like every alternative one we’ve heard, carries a huge load of baggage. It’s difficult to come up with a solution that isn’t worse than the current problem.

It will be interesting to watch how the particular Altera/Tabula/Achronix/Xilinx situation plays out – if it even turns out to be a situation at all. And, it is nice to hope that someday our IP laws will begin to catch up with the reality of technology and engineering employment. Engineers deserve ownership of our own brains, and we deserve to be rewarded in a way that’s commensurate with our contributions.


11 thoughts on “Selling Your Brain”

  1. Pingback: seedbox
  2. Pingback: DMPK Studies
  3. Pingback: kari satilir
  4. Pingback: Learn More
  5. Pingback: Stix Events

Leave a Reply

featured blogs
Dec 1, 2023
Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users. T...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Energy Storage Systems
Increasing electric vehicle sales, decreasing battery sales, and a shift in energy consumption has made energy storage systems more important than ever before. In this episode of Chalk Talk, Amelia Dalton chats with Gijs Werner from Amphenol FCI Basics about the functions and components involved in commercial energy storage systems, residential energy storage systems and EV charging stations. They investigate the qualifications needed for connectors in energy storage systems and what kind of connectors Amphenol FCI Basics offers for your next energy storage system design.
Apr 3, 2023