feature article
Subscribe Now

Cheap Chips

ASICs for the Rest of Us

We all know the story: ASIC starts are falling as the costs of the design tools, the mask sets and the manufacturing process are all going through the roof. Don’t even think about starting an ASIC design unless your budget is measured in millions of dollars. The development process is going to require a large team of engineers. The only way you can make money with an ASIC is to sell many hundreds of thousands of devices, and that normally implies consumer markets. But ASICs take months to years of development – a development cycle that can be longer than the product life of a consumer product, which is typically measured only in months.

But over the last few weeks, I have been talking to people who will happily talk about ASICs that cost only tens of thousands of dollars to design and begin to manufacture, and have a return on investment measured in months.  How come there is such a huge difference?

Let’s start with why you might want an ASIC. It could be that, of the many functions that you are carrying in a microcontroller, you feel you can speed some up by moving them to hardware, or you feel you need to add new interfaces. You may have several individual devices on a board and you want to improve speed and reliability or reduce Bill of Materials costs, or you may want to create a smaller footprint. By pulling the functions of multiple devices into a single ASIC, you could achieve these things.

To take a specific example: you are part of the small electronics team in a company making consumer white goods (washing machines, refrigerators etc). The control system for a washing machine is a microcontroller and some peripherals on a small pcb. The peripheral chips are often Analog Mixed Signal (AMS) devices interfacing the microcontroller to sensors and controls – for example, sensing water temperature and turning on or off a heater. Your boss decides that she wants to add wireless connectivity so that the washing machine can be controlled and monitored from a smart phone. You don’t know much about wireless, and, although there are devices you could add to your pcb, you are already pushing the space budget on your board. If you use a bigger board, the overall machine design would need some changes for it to fit – not a cheap task. Your volumes are going to be measured in thousands rather than millions, and you need to retain the microcontroller capability to allow you to produce variant models though software.

This process is going to be repeated many times over as the rise of the Internet of Things (IoT) is going to add communication to many currently stand-alone devices and as new devices will be created specifically for the IoT by companies not normally thought of as electronics designers.

One way to resolve the problem is to put all the separate devices into an ASIC. The first thing to realise is that you don’t need to go to the bleeding edge of process technology. For a start, you are, by definition, going to have sections of AMS, which pull you back at least one or more process nodes. But there are good reasons for going to a process no more advanced than 180 nanometres. As this is a very mature process, there are vast quantities of proven IP, both analog and digital. The ARM Cortex-M0 processor is optimised for 180 and gives you full 32-bit capability in only 12,000 gates, potentially leaving acres of space on the chip for the other functions. Manufacturing capacity at this level is widely available. The process technologies are now rock solid, and, as the manufacturing equipment has already more than paid for itself, foundries are offering very competitive pricing to keep their fabs loaded.

For the same reasons, the mask makers are also very competitive at this node, and you don’t have to cope with issues of multiple patterning and its related mask costs at 180. A cheaper road may be to not have your own mask set, at least initially, and to go instead for a space on a multi-project wafer (MPW) where a consolidator, such as MOSIS, puts multiple devices onto a single mask set, to run in one of the leading foundries. Depending on your needs, you might just prototype your device or move into low volume production runs. In Europe, Europractice, as well as supporting universities, also offers MPW services to industry, coordinated through IMEC in Belgium and the Fraunhofer Institute.

But you still have the issue of designing the device. One route would be to buy lower-priced tools. Tanner EDA has a suite of tools that provide much of the capability of the big names for a fraction of the cost. As their European distributer, Paul Double of EDA Solutions, explained, “At the smaller process nodes, the problems of designing are much more complex.” For example, timing at 25 nano is not just a matter of gate delays; even the length of the interconnect wires have to be taken into account. There are considerably fewer gates on the chip at the older nodes. This allows Tanner to support the older nodes with simpler, and less expensive, tools.

But you don’t need to do the design yourself. There are contractors you could hire who can supply the skills you don’t have in-house. Or, alternatively, you could use a specialist design company. One I spoke to was the S3 Group in Cork, Ireland. Like many of the other companies, they try to be as flexible as you need, starting from helping you turn the idea of “Something like this with a bit of communication added” into a detailed technical specification, and then going on to give advice and help in choosing IP, carrying out the design – including creating the test programme – selecting a foundry or MPW, and even providing help with test and assembly. Using such a company simplifies your task, and you are benefiting from their experience on many other projects, but it does, of course, add to your costs. The trade-off is relatively simple: are you confident enough in your in-house skills to do all these tasks, or are you prepared to pay for someone else’s skills?

Then there are the players in this field who take over the entire project, in effect taking in the design and delivering your volume chips. You don’t have to worry about how the chips get from the foundry to the assembly contractor and then from them to you. The Europractice partners offer consulting on this, and commercial companies with whom I have had contact include e-Silicon, Swindon Silicon Systems, and Open Silicon, all of whom offer slightly different services at a wide range of process nodes.

Now, of course, I hear you say, what about a Field Programmable Device, perhaps the Xilinx Zynq or Altera’s SoC families? These come with hard ARM cores and areas of programmability, backed by a mass of IP. Why mess around with foundries, packaging companies and all that stuff?

AMS is one reason. Xilinx has some resources, mainly analog-to-digital convertors. If you can get by with this, then it might be helpful, but there are other issues. These devices are expensive for anything above relatively low volumes, they are physically quite big, and you are restricted in your packaging. If you are working on a device for the IoT, you almost certainly don’t want the size of packaging and the number of pins that are intrinsic to even the smallest of these devices. And of course you want the minimum of power consumption

It does look as though you can now seriously consider an ASIC for even quite small quantities. The recipe is simple. Take an ARM Cortex core, with its massive eco-system of development tools and software, add a mix of peripherals made from proven IP, stir with carefully chosen partners, and you have your very own ASIC- just ready for IoT and a range of other activities.

20 thoughts on “Cheap Chips”

  1. Can you still do the “sea of gates” ASIC. The foundry would build an ASIC with lots of gates and leave the top metal layers off for later. The task was putting together the top layer (or 2) of metal interconnect.
    It cost $80-100K in NRE 10 years ago. Much of that was packaging cost. Per part cost was under $2, depending on the package and number of pins.
    The power savings for a static logic design were considerable. We built framers and encryption engines, so not trivial designs.
    The speed and power were better than an FPGA, but not as good as a full ASIC.
    I think the tool cost for the design and RTL tools was almost as much as the NRE, but it was spread across 2-3 chips before a tools upgrade.
    Does anyone still do this sort of ASIC? It seems like a secret in the industry.

  2. While Xilinx has abandoned the lowest end of programmable logic Altera has a low cost, low power, DSP capable device with analog data inputs (AMS). I work at Altera so I currently can’t tell you all the great features of this device but it has all the stuff you say you can’t buy. I highly encourage people to get in touch with Altera to see all the great features of this IoT device.

    From http://www.altera.com


    “Analog functionality for sensing board environment allows integration of power-up sequencing and system monitoring circuitry into a single device.
    High I/O count and software based system management using the Nios II soft processor enable board management integration in an advanced, reliable single-chip system controller.”

  3. It’s an age old question, what to select for your design? ASIC, FPGA, standard parts, ASSP etc. Each will have its merits for a particular design and market requirements, that’s why these solutions still exist, there is no one panacea.

    What is important though is that designers do not generalise, e.g. ASIC’s are expensive, FPGA’s do not offer low power, etc. Check out each solution for your design, it becomes obvious quickly if it is not a technical and commercially viable solution.

    Vendors will be happy to help you with this. A successful design is good for everyone.

    Remember, technology is constantly moving, so even if prior designs were best suited to one particular development route, this can change.

  4. carlwh- I agree. But designers do generalise which is why ASIC is often not even thrown into the mix because of the perception of difficulty, time and cost.

  5. Another alternative is the Agile ASIC™ solution from Triad Semiconductor (yes, I work @Triad, http://www.triadsemi.com).

    Triad is a full-service turnkey provider of analog and mixed signal ASICs. Our services include the turnkey development of custom ASICs as well as productization and long-term supply chain management.

    We design custom ICs for you and provide you with packaged, tested parts.

    Our design team is comprised of seasoned professions and we support customers in the defense, medical, industrial, automotive and consumer markets.

    Unique to Triad, we can deliver “Cheaper Chips” and “Faster to Market Chip” utilizing our Agile ASIC™ approach. An Agile ASIC contains full-custom, high-performance IP resources that are then overlaid with Triad’s patented routing fabric. Your full custom ASIC is initially fabricated and here’s where the magic happens…

    When you need to make a design change in an Agile ASIC (and greater than 95% of all mixed signal ASICs need multiple spins to get production ready) all that needs to be changed is a single via layer to make interconnect and functionality changes throughout the entire chip.

    WTMFY – What That Means For You:

    1) Respins to new packaged parts in 4-6 weeks
    2) No waiting for MPW schedules
    3) Respin costs are minuscule compared to full-custom respin costs
    4) Your prototype devices are production ready silicon. No retooling charges or time wasted going from an MPW mask set to a production mask set

    Yes, you get full custom performance but without the cost and schedule overruns typical of traditional full-custom ONLY approaches.

    I’m always available to talk ASICs, @reidwender

  6. Dick, thanks for the brilliant overview.

    I think the ASIC route is often disregarded for a couple of reasons:
    For Digital the cost is not really known and the forum is missing to help there.
    For analog the trust factor comes in.

    We are representing companies in this field and esp. for complex analogue, where a customer often does not have a choice as it is the only option for performance of the analog side.
    Here you ask for the design references of the design house, and might even contact the end customers to get a better feeling.

    The smallest requirement we had was about 30 gates:
    Only 1000 to 2000 pieces, digital
    Why look at ASIC?
    Any FPGA will be too big and too power hungry
    Building the same with chips takes too much space.
    It was a safety function, so very critical.
    It was not much more expensive in a well selected ASIC run than as CPLD/FPGA solution.

    One aspect we see is the mobile phone factor – introduce new features very often, upgrade in the field, deploy quicker, accept more design risk – means FPGA.

    For many people with lower volumes it is difficult to collect all of the info to come to a clear decision – living with an FPGA is the safer approach then.

    There is also the MIXED OPTION: a microcontroller with FLASH to have the flexibility, the ASIC with the additional features. And you can extend or even correct features in software.

  7. Pingback: pax 3 buzzing
  8. Pingback: D/s
  9. Pingback: GVK Biosciences
  10. Pingback: DMPK Studies
  11. Pingback: zdporn
  12. Pingback: Bolide
  13. Pingback: IN Vitro ADME
  14. Pingback: satta matka

Leave a Reply

featured blogs
Jul 12, 2024
I'm having olfactory flashbacks to the strangely satisfying scents found in machine shops. I love the smell of hot oil in the morning....

featured video

Larsen & Toubro Builds Data Centers with Effective Cooling Using Cadence Reality DC Design

Sponsored by Cadence Design Systems

Larsen & Toubro built the world’s largest FIFA stadium in Qatar, the world’s tallest statue, and one of the world’s most sophisticated cricket stadiums. Their latest business venture? Designing data centers. Since IT equipment in data centers generates a lot of heat, it’s important to have an efficient and effective cooling system. Learn why, Larsen & Toubro use Cadence Reality DC Design Software for simulation and analysis of the cooling system.

Click here for more information about Cadence Multiphysics System Analysis

featured paper

DNA of a Modern Mid-Range FPGA

Sponsored by Intel

While it is tempting to classify FPGAs simply based on logic capacity, modern FPGAs are alterable systems on chips with a wide variety of features and resources. In this blog we look closer at requirements of the mid-range segment of the FPGA industry.

Click here to read DNA of a Modern Mid-Range FPGA - Intel Community

featured chalk talk

USB Power Delivery: Power for Portable (and Other) Products
Sponsored by Mouser Electronics and Bel
USB Type C power delivery was created to standardize medium and higher levels of power delivery but it also can support negotiations for multiple output voltage levels and is backward compatible with previous versions of USB. In this episode of Chalk Talk, Amelia Dalton and Bruce Rose from Bel/CUI Inc. explore the benefits of USB Type C power delivery, the specific communications protocol of USB Type C power delivery, and examine why USB Type C power supplies and connectors are the way of the future for consumer electronics.
Oct 2, 2023