It’s been a few weeks since the annual gathering of the world’s semiconductor lithography illuminati, put on by SPIE. And we’ve covered a few of the specifics, from DSA to EUV (including some interesting exposure results and a bit of a 4/1 headfake – sorry about that) to LER. Which almost rounds out the stories I gathered from the event (with one more coming).
And, for all the drilling we do into the details of these technologies and how they’re progressing, it’s good to take a step back occasionally to review the big picture. So that’s what we’re going to do today. Some of the food for thought that gives rise to this comes from the specifics of the various conference sessions; other comes from a conversation I had with Applied Materials’ DMTS Chris Bencher, and yet more from observances around the web and elsewhere.
Let’s start with a stupid question: what the heck problem are we trying to solve here, anyway? You might think the answer is trivial: we’re trying to figure out how to pattern features smaller than we can do today.
And that’s not quite the right answer: we’re trying to figure out how to pattern features smaller than we can do today in a manner that allows the semiconductor industry to generate a profit. We have lots of technology to choose from; it’s just that none of it can yet provide the right economics.
We’ve been living in an era with a Single Way to Do Lithography for a long, long time. And we’ve been looking to EUV as the Great Savior that will keep us in that era. But I don’t think so. Things are getting messy, and there will be options.
In theory, as our features get smaller and smaller, we would simply dial down the wavelength of light used to image our wafer patterns. But, as with any delicate recipe, you don’t want to keep changing things. If all the equipment and materials used in the process are optimized for a particular wavelength – say, 193 nm, then it’s easier to stay there and make more nominal changes as we go from node to node.
Of course, umpteen years ago, that shrinking-wavelength concept was extrapolated to another big jump down into extreme UV wavelengths. And we’ve been talking about that ever since, while, in the meantime, 193 nm, with the addition of a drop of water (193i – “i” for “immersion”) and some incredible optical tricks, has managed to carry us way farther than had ever been expected.
EUV has captured an enormous amount of investment, and it’s taken so long, and it’s still not here, although there is progress. But it’s been the subject of conjecture and pessimism for some time. Even today there are opinion pieces wondering whether it will ever be here and what the alternatives are.
But here’s where we leave the Single Solution era: if or when EUV happens, it’s not like we’ll give up all our existing 193i stuff and move right over. EUV is expensive – it’s just supposed to be less expensive than some of the alternatives in a few really tight places in the mask stack. So, especially if throughput is iffy, EUV is going to be used only where absolutely necessary. For those layers that are more forgiving, we’ll use the cheapest process available, which won’t be EUV. 193i has a long life ahead.
So even if EUV succeeds, the overall processing of a wafer is likely to result from a mix of old and new lithography. No more Single Way to Expose.
What about alternatives? You see discussions of DSA, for example, as being a potential replacement. Then there’s e-beam, and there are still options open to us with 193i. In theory, nano-imprint lithography (NIL) might have a play here, but it’s not anything that anyone seems to be investing in other than for specialized cases like hard drives, so I’ll leave it to the side.
Let’s start by reviewing the challenging things we need to pattern and then come back to the options.
Historically, the kinds of features to be patterned onto a wafer have been more or less random and irregular. Yes, for the most part, angles have been limited to 90° (occasionally 45°), but creating the features has been tantamount to solving a topological puzzle.
Back when I started in the industry, we were just getting to two layers of metal. With that kind of limit, you have to be clever and have good visualization skills to get everything where it’s supposed to be with a minimum of jogging and as few jumps between metal layers as possible.
What used to be done by hand is now done by tools, but automation from that era would try to replicate or improve upon what was being done by hand under the two-layer-metal constraint. So even once that constraint was lifted, we’ve still done layout more or less the same way. It was only a few years ago when a few folks started thinking that, in the long term, we’d need to start laying things out differently.
That different way is “1D gridded” layout. The “1D” part of that means that any particular layer of metal would have lines going in only one direction – either up/down or left/right, and layers would alternate directions. This eliminates many of the challenging effects that oddball shapes have on how light exposes the wafer.
Some companies have already started doing layout this way, but many have not. So we’re still working with the legacy of two-layer constraints. But if we push forward under the assumption that this will be the way of the future, then we can over-simplistically say that layout will consist of three things:
- Run a bunch of parallel lines.
- Cut those lines to define specific features (e.g., fins) or runs (i.e., metal lines).
- Create holes in intervening layers to connect things. These might be contacts (if to silicon) or vias (if metal-to-metal).
I say, “over-simplistically” because it seems like, for every basic mask layer, there end up being several steps required to handle the details. Fortunately, those extra details are beyond the scope of this piece. (“Fortunately” because they’re also beyond my current ken.)
So the questions then become,
- What’s the best way to create parallel lines?
- What’s the best way to cut those lines?
- What’s the best way to create holes?
The contenders for making parallel lines at this point appear to be double- (largely SADP), triple-, and quadruple-patterning (SAQP); EUV; and DSA. Somewhere down the line, carbon nanotubes might have a role here, but that’s too speculative, and I’ll leave that out of further consideration for now.
The contenders for cutting lines would appear to be EUV and complementary e-beam lithography (CEBL). Why not multiple patterning? Well, I could be all wet here, but, for the most part, multiple patterning seems useful for placing multiple features closer together than could be done with a single exposure. With a cut mask, it may not be so much about how close together the cuts are, but how small they are. That said, an all-multiple-patterning solution might eliminate the whole need for a cut step simply by allowing small lines to be patterned very near each other.
The contenders for holes appear to be the same as those for lines: multiple-patterning, EUV, and DSA.
So one of the big questions you hear a lot these days is, what if EUV doesn’t happen? That leaves multiple-patterning and DSA as the leading contenders for laying down lines and holes, and it leaves CEBL as the way to do cuts.
But DSA, while making huge strides, isn’t ready yet either. And CEBL poses throughput issues that would need attention if all eyes turned from EUV to it.
Which leaves multiple-patterning. Which is expensive. Relatively.
Or is it? In fact, Mr. Bencher contends that “SADP/SAQP will rule” and that all else will be niche. And, while you hear most people quiver at the thought of having to do lots of multiple-patterning, he says that “SAQP is very cost-effective.” Not exactly what I’m used to hearing.
He bases this on the fact that some companies jumped on the technology quite some years ago. One of those “we’re going to need this eventually, so might as well bite the bullet now before it’s urgent” things. They changed design styles, moving to 1D gridded, and have now accumulated about seven years’ worth of experience with SADP. And they’re finding the transition to SAQP not so difficult.
If you’re still doing design the old way, it’s probably going to seem like a much bigger deal.
All of that said, there’s still the possibility that some of the leading-edge nodes turn out not to be economical, or at least not for a while. That would stop this freight train that’s been barreling down the track from micron-dimensions to the-next-smaller-step.
Would the world come to an end? It’s said that classical capitalism needs constant growth to succeed, and, while we know that nothing can grow forever, we conveniently assume that this will be a problem far down the line. Likewise, we’ve lived in a world that assumed constant migration down the dimensions. (Yes, I’m doing an experiment here – can I make it all the way through this article without referencing M… um… that Law?) If that’s no longer true, is that the end of semiconductors as we know them?
Well, first of all, at this point, we’re talking economics more than technology. So Mr. Bencher suggests that we might come to a lull rather than a crashing stop. That would give time for the economics to catch up. But he says that, even if we paused for a while on the 10- or 14-nm node, he still sees two nodes’ worth of IC progress available by improving design techniques without moving to a new node.
The other question that looms, if you insist on thinking about it, is, “Can the semiconductor world survive an end to the rush to smaller geometries?” Seems like it should be able to, in some fashion. After all, how many other industries have such expectations? Look at the auto industry: there’s been no rush to improve fuel efficiency (seems that’s the only metric for progress; it’s not like they’re trying to shrink cars or make them faster). In fact it’s been quite the opposite: up until recently, they’ve opposed any requirements to improve it.
Much industry would appear to be similar: get the operation going until it’s smooth, oppose any changes, and go play golf now that the hard work is done. Oh yeah, the competition thing: lobby to make laws that make it harder for outsiders or newcomers to get a foothold. Problem solved.
OK, that might not quite be fair (is it?), but it’s very different from the constant chase we chipheads live in. Could we survive if the pace and dynamic changed? What if what we’ve been seeing is simply the inflation period after our Big Bang, and, at some point, we’ll head into a more relaxed expansion regime? Could we do that?
Well, the constant shrinking of features has bought us three things:
- Cheaper silicon, so we can use it in more applications.
- Integration: we can stuff more onto a single chip.
- Speed, although that’s pretty much been exhausted. Now it’s efficiency and lower power, and the process migration actually goes against that. We’re getting processing speed through multicore these days, and that takes us back to the integration benefit.
If we come to the end of the ride, if the goal isn’t faster/cheaper/smaller, then does our raison d’être evaporate? It would seem to me that, since other industries survive without this dynamic, ours should too. It’s not like we would suddenly no longer need ICs. But I certainly can’t see the manner in which the structure of the industry would change, as indeed it would have to.
Fortunately, we have now entered the realm of speculation, since this eventuality is likely still many, many years away. And I’ll leave speculation to Wall Street. It’s an interesting question to ponder, but, happily, it doesn’t demand a quick answer. (I don’t think…)
More immediate possibilities are that (1) lithography is going to change from one to a mix of techniques for different products and different layers on those products, and (2) we may do something of a stutter-step a couple of nodes hence. The sense I get is that we can survive that if it happens; we’ll just need to do things differently.
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