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The Secret Ingredient

Altera and ARM Roll FPGA/SoC Tools

We’ve talked a lot about the awesome combination of ARM-based processors with FPGA fabric in these pages. The power of a state-of-the-art dual-core ARM matched with the almost infinite flexibility of an FPGA brings to mind so many fantastic possibilities that it’s hard to know where to begin. This combination truly represents a new breed of SoC that is capable of solving a great number of problems that could never be addressed before, and with Altera and Xilinx both now marketing such devices, the excitement has only just begun.

We have also discussed (in a different tone of voice, of course) the myriad challenges posed by this new architecture. In the hardware, we see a platform that is capable of delivering on the Grand Vision of software/hardware co-design – where each function is carried out by the chip in whichever mode (software or hardware) best suits the design goals of power, performance, and cost. However, being able to realize that vision will take a lot more than hardware – it will take tools and IP the likes of which the industry has not yet seen. 

We now have the best machine in the world, but no way to program it.

Altera and ARM jointly announced a new set of specialized tools for programming (and more importantly, debugging) Altera’s just-released SoC FPGAs. If you didn’t believe already that tools were the bottleneck in market acceptance of ARM+FPGA SoC technology, you have to look no further than this announcement. With the new Cyclone V SoC devices now shipping, Altera chose to focus their announcement on the tools used to design with them. ‘Nuff said.

OK, not really ‘nuff said – you know us far better than that. The interesting thing about this announcement is that Altera and ARM have collaborated in developing and deploying a sophisticated set of tools for programming and debugging these devices. The two companies claim that this is both the first “FPGA-Adaptive” software tool kit and the first vendor-specific version of ARM’s Development Studio 5 (DS5)

So, one might ask the question – why do we need special tools? After all, we’ve had FPGAs for a long time (and there are clearly lots of tools for those), and we’ve had ARM processors for a long time (and ARM has a proven set of development tools handling that part of the operation). What is it about these new devices that demands new tools?

Of course, people have been parking FPGAs next to their ARM-based SoCs for a long time. We’ve had adequate tools for both, but the real promise of these FPGA+CPU devices is not just cutting two chips down to one. It’s providing an integrated solution that allows functions to be smoothly partitioned and debugged across hardware and software implementations. It’s about providing an SoC with an almost infinitely-variable collection of peripherals and having that SoC behave as well as an off-the-shelf SoC from a programmer’s perspective. It’s about not having to maintain two engineering teams that don’t talk to each other, working in different domains in different disciplines with different tools. It’s a grand unification of epic proportions – but it is 100% reliant upon tools to make it happen from a design perspective.

That’s why the Altera/ARM tool announcement is the headline, instead of the fact that Altera is now shipping Cyclone V SoC FPGAs. The silicon is awesome and necessary and available, but nobody will want it unless they understand that there is a great, integrated tool chain in front of it. 

Without this new tool suite, we’d have to have 2 sets of tools connected to our Cyclone V SoC FPGA via 2 separate JTAG connections. Neither tool would be able to visualize what was happening across both the FPGA and CPU domains. We couldn’t cross-trigger and correlate events between FPGA and CPU. In the “normal” ARM SoC debugger, we wouldn’t have the ability to adapt to the variety of peripheral configurations that the FPGA fabric enables. In short, we would be no better off than if we still had 2 chips sitting next to each other. 

The ARM Development Studio 5 – Altera Edition solves all of these issues. A single Altera USB-Blaster connection links your device to the tools. The system automatically creates register-level views for FPGA peripherals so you don’t have to go searching a memory map to find out what’s going on with the peripheral connection. A non-intrusive trace of CPU software instructions cross-correlates with application and FPGA hardware events. Similarly, you can set complex cross-trigger events between CPU and FPGA domains. You can do simultaneous debug and trace on the two Cortex A9 cores and any “CoreSight” enabled IP blocks in your FPGA fabric.

This cross-correlated and event-driven debug is important when debugging multi-core applications, and it’s doubly important when you’re dealing with a variable set and scope of FPGA-based peripherals and accelerators. In addition to these debug features, you can also do statistical analysis of software and bus-traffic load spanning the CPU cores and the FPGA components.

Behind this tool suite are some interesting devices – similar in most ways to archrival Xilinx’s Zynq platform. Altera has “SoC’d” both their Cyclone and Arria lines (the low-cost and mid-range FPGA families), so versions of both of those families will be available with either single- or dual-core A9 processing subsystems. The first of the Cyclone V FPGA SoCs are shipping now, with the remainder scheduled to arrive over the coming months.

The devices can be configured at the system level using Altera’s Qsys tool – which allows the selection and connection of virtual peripheral IP blocks. Altera also provides a virtual platform that allows software developers to begin working before the actual hardware design is finished, so hardware and software parts of your project can proceed in parallel. This is particularly important since software is often the longest part of embedded system project schedules.

It will be interesting to watch the adoption of this new class of FPGA+CPU devices. With multiple vendors driving them into the market, we have yet to see whether the traditional embedded development community will embrace them as the powerful alternative to conventional (non-FPGA-enabled) SoCs. Of course, design teams that already have FPGA experience will welcome and apply these devices in a wide array of interesting applications, but the key to this becoming a breakout technology is seeing it expand beyond the bounds of normal FPGA-friendly design teams. 

Let’s see what happens.

2 thoughts on “The Secret Ingredient”

  1. Can someone tell me why this CPU + FPGA chip is so exciting when we had something, albeit smaller, years ago (1999) in the form of the Atmel AT94K FPSLIC that, sadly, just seemed to fizzle out? Is it all about size or is it because the names of the elements involved started with the wrong sort of “A”??

  2. @dysonwilkes,

    OK, I’ll tackle that one.

    First, these devices (Zynq, Cyclone V SoC, SmartFusion2) have not yet “caught on”. There is a very real chance that they’ll just “fizzle out” in the marketplace just as you’re describing.

    I don’t think they will, though.

    Here’s my reasoning:

    1) 2013 is not 1999. The Newton fizzled out, but we have smartphones. The Osborne fizzled out, but we have laptops. The list goes on and on – the market takes ideas on its own calendar, not ours.

    2) Size, as you say is a huge difference. An 8-bit microcontroller with 40K “gates” of FPGA logic is really a very different thing from dual-core ARM A9s with hundreds of thousands of LUTs of FPGA logic, tons of memory, and multi-gigabit SerDes IO.

    3) Because of #2, the application space is completely different. These devices can run full-blown operating systems, accelerate key algorithms to supercomputer speeds, and blast data in and out at staggering speeds. They can swap around peripheral sets on the fly. With the bandwidth they provide between the “FPGA” part and the “CPU” part, they can do things that no combination of discrete CPUs plus FPGAs can do. This is not a simple “integration” play where 2 chips are replaced with one.


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