feature article
Subscribe Now

So Long and Thanks For All The Glue Logic

25 years ago FPGAs were the latest and greatest new thing. They were, by replacing glue logic, going to speed up the design of systems, simplify Bills of Material and generally make life easier. Actel ran an ad with the headline “Idea at Breakfast – In Production by Dinner.” Over time, FPGAs have got bigger, faster, and more complex to design. And while they have not replaced ASICs and SoCs, something their advocates were predicting a few years ago, the numbers of ASIC and SoC design starts is certainly not growing at anywhere near the rate of FPGA design starts. Design systems have evolved into tool chains: instead of designing with schematics and dragging and dropping macros of a few gates each, FPGAs now need complex design systems with RTL – just like real ASICs and SoCs. And it is the time and complexity of design that is a potential Achilles heel for future FPGA growth.

But what are the alternatives to FPGAs? I think there are at least two: Xilinx’s Zynq (and the forthcoming Altera alternative) and the xCORE from XMOS.

As there isn’t a great deal of material on the Altera approach yet in the public domain, I’ll concentrate firstly on Zynq. This doesn’t mean that their approach is better than Altera’s, just that Zynq is available. To refresh your memory, instead of having an FPGA with a hard-core CPU, Zynq is a CPU, a chunky ARM dual-core Cortex-A9 running at up to 1GHz, with an AMBA bus to communicate with a wide selection of peripherals plus a big area of programmable fabric to add more peripherals and other capability.  It started shipping a year ago, and Xilinx claims that the Zynq “design pipeline [is] now equal to FPGA families.” This is a very strong claim. At first, cynically, I thought the claim was partly accounted for by the cost of a Zynq device – but then I checked and saw how much you have to pay for some of the top-end FPGAs.

Zynq seems to be going (and this is partly an assumption on my part and not Xilinx information) into sockets that would otherwise be filled with ARM-based microcontrollers from the mainstream silicon companies. A big advantage is that the device can be tailored exactly to the application’s needs for peripherals rather than having to fit into the (admittedly normally very large) selection of versions that the company has chosen to offer. And with the programmable fabric on chip, instead of using a processor and an FPGA, you can use just the Zynq, reducing BoM and board area and possibly improving performance, since there is no chip-to-chip communication.

Design tools for Zynq are in the Vivado integrated design suite, which was launched last year and is a “clean sheet of paper” build which has cost Xilinx a vast amount of time and money. The IP available for Zynq is not yet at the “drop it in and it works straightaway” stage. (But then, neither is it for ASICs and SoCs). But third parties are creating IP, as is Xilinx. Since the processor is an ARM core, there is a lot of software and a wide choice of development tools out there. Only a few days ago, Green Hills announced that it had joined the Xilinx Alliance, specifically to offer security- and safety-certified tools for Zynq, including the Integrity RTOS and Multivisor virtualisation technology and the Multi IDE.

And with the announcement of its 20nm road map, Xilinx made it clear that Zynq is going to get bigger and faster, with possibly different processor options.

xCORE is a totally different approach. XMOS is a spin-off from the University of Bristol’s Department of Computer Science. It has been around for seven years and has quietly built a base of over 1000 customers for the xCORE products.

xCORE has been described in a number of different ways over those seven years. Recently, as a part of what is effectively a company re-launch under a new CEO, the description has been changed to “multicore microcontroller.” An xCORE device contains one, two, or four tiles, each of which has eight 32-bit logical processor cores, which run programs written in high-level languages. (A tile is rated at 500 MIPS when running at 500 MHz.) Logical processor cores appear to be separate parallel processors, with their own registers. (They share other resources on the chip.) The xTIME timing and synchronization technology assigns a slice of the processing resource to each logical processor core – normally up to 125 MIPS.

The xTIME technology balances processing loads and also is part of the delivery mechanism for completely deterministic timing – program performance is totally predictable, making the devices attractive for developing real-time applications.

Unlike a “normal” microcontroller, there is no long list of family members, each with its own selection of hardwired peripheral interfaces. Instead, xCORE has extensive logic that can be programmed to be an interface, either on its own or with a logical processor core. A growing family of IP, called xSOFTip, includes USB, Ethernet, and serial ports, as well as signal processing and protocol functions. Since the protocols are software defined, xCOREs can be used to develop products for emergent standards, and an example of this is the company’s work on supporting AVB (Audio Video Bridging), an Ethernet protocol that includes, among other things, synchronisation between the different devices, such as speakers, on a network.

The xSOFTip library also has a range of other functions, such as audio DSP, display and memory controllers, and peripheral interfaces. And, just to add to the mix, there are reference designs, with their own boards and starter kits, and a new family of sliceKITs. These are based on a core board, already populated with a 16-core device, and add-on boards already set up for specific functions, such as JTAG, power supply, Ethernet, and other interfaces. The development environment, xTIMEcomposer development suite, is free to download, is eclipse compatible, and provides a nice sandpit to explore xCORE.

One area where XMOS has made significant penetration is in audio, particularly in audio-streaming applications for high-end consumer and professional applications.

The reason I have gone into more detail on xCORE than I have on Zynq is that, as a reader of FPGA Journal, you are almost certainly aware of Zynq. After all Xilinx has been pushing the product and its variants for more than two years. But do you think of either of these products when you are looking at your next project? Or do you just reach for the familiar “standard” FPGA?

One factor that might make you consider xCORE is price. While DigiKey is listing Zynq at a starting price of $272.50 for a one-off purchase, the same distributer is listing xCOREs starting at $7.00. With free development software and boards starting at under $50 on DigiKey, isn’t it worth at least having a play?

Now – I have to declare an interest. I have been following XMOS since it was founded and have known one of the founders for over 30 years. And they are British, and we all like to cheer for the home team. I have even done some work for them in the past. But, with all that, I think I have rationally reached the conclusion that both the Zynq platform and the xCORE offer some very interesting options to a conventional FPGA and microcontroller coupling in a wide range of systems and applications.

16 thoughts on “So Long and Thanks For All The Glue Logic”

  1. … very nice article. I would like to add that XMOS basically grew out of the Transputer technology, some are the same people, technology probably without offending any older patents, but a similar way of thinking.
    Additionally I would like to add 2 other approaches. One is greenarrays at http://www.greenarraychips.com/home/products/ 144 cores at very low power on one chip at $20, IO in software like xCORE and a new French company, the name escapes me, who are trying to take part of the FPGA market using DSP technology.

  2. Pingback: GVK Bioscience
  3. Pingback: DMPK CRO
  4. Pingback: Bdsm positions
  5. Pingback: mondo sonoro
  6. Pingback: Political Diyala
  7. Pingback: iraqi geometry
  8. Pingback: click here now
  9. Pingback: satta matka
  10. Pingback: Coehuman diyala

Leave a Reply

featured blogs
Nov 25, 2020
It constantly amazes me how there are always multiple ways of doing things. The problem is that sometimes it'€™s hard to decide which option is best....
Nov 25, 2020
[From the last episode: We looked at what it takes to generate data that can be used to train machine-learning .] We take a break from learning how IoT technology works for one of our occasional posts on how IoT technology is used. In this case, we look at trucking fleet mana...
Nov 25, 2020
It might seem simple, but database units and accuracy directly relate to the artwork generated, and it is possible to misunderstand the artwork format as it relates to the board setup. Thirty years... [[ Click on the title to access the full blog on the Cadence Community sit...
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...

featured video

AI SoC Chats: Protecting Data with Security IP

Sponsored by Synopsys

Understand the threat profiles and security trends for AI SoC applications, including how laws and regulations are changing to protect the private information and data of users. Secure boot, secure debug, and secure communication for neural network engines is critical. Learn how DesignWare Security IP and Hardware Root of Trust can help designers create a secure enclave on the SoC and update software remotely.

Click here for more information about Security IP

featured paper

Streamlining functional safety certification in automotive and industrial

Sponsored by Texas Instruments

Functional safety design takes rigor, documentation and time to get it right. Whether you’re designing for the factory floor or cars on the highway, this white paper explains how TI is making it easier for you to find and use its integrated circuits (ICs) in your functional safety designs.

Click here to download the whitepaper

Featured Chalk Talk

General Port Protection

Sponsored by Mouser Electronics and Littelfuse

In today’s complex designs, port protection can be a challenge. High-speed data, low-speed data, and power ports need protection from ESD, power faults, and more. In this episode of Chalk Talk, Amelia Dalton chats with Todd Phillips from Littelfuse about port protection for your next system design.

Click here for more information about port protection from Littelfuse.