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I Can Has Roadmap?

The Common Platform Alliance Goes to 14 nm and Beyond

It’s a fine marketing line: pick a strong, simple message and reinforce it without smashing it into your prospect’s face. You want to direct someone’s actions without them feeling like they’re being directed.

Most conferences have a cacophony of messages. I’ve been asked many times, “What are you seeing at [name your conference here]?” and I’m sometimes stumped for an answer because I’m seeing so many different things. Of course, most conferences are put on by organizations whose stake is simply in putting on a conference, so the messages really come from the exhibitors or presenters, and attempts by the organizer to unify a theme seem lackluster at best.

I’ve been to only a couple Common Platform Alliance (CPA) Technology Forums, and, like many vendor-owned conferences, there is better control and alignment of content.  But it wasn’t until this year’s event that I realized how transparent the messaging seemed to me – and not really in a bad way. I came away thinking, “Aha, this is what their prospects have been asking.”

Last year, they were clearly beset with the gate-first/gate-last issue, and all messages were aligned with demonstrating that their technology worked and was production ready. This year, I would speculate, their prospects have been asking, “OK, that issue is behind us. But do you really have a roadmap for the future?” And so this year’s event was all about technology to 14 nm and beyond.

A lot of the fundamental coverage was provided by the IBM side of the CPA triangle. While many of the elements involved in the roadmap are items we’ve discussed here already, we’ve done so in a scattershot approach, while these conference sessions provided more of an overview, placing various technologies into perspective. There are also pieces we haven’t covered yet, and we will need to do so as they emerge from the labs.

While the range of topics in Gary Patton’s keynote presentation included both chips and packages, I’ll focus on the chip aspect here, pulling both from that keynote and from more detailed presentations in the afternoon.

In the discussion of devices, the biggest obvious topic centers on lithography, since that’s how stuff gets printed and that’s where a lot of uncertainty lies. At the 14-nm node, everyone is hoping for EUV to be in place. It shortens the exposure wavelength to the point where many of the tricks in use today are no longer needed, but it changes everything about mask exposure – it’s the opposite of an evolutionary or incremental change.

EUV may well play out as hoped, but, as we’ve seen, no one is counting on it completely. Alternatives start with the so-called sidewall image transfer (SIT) approach, which gets a line multiplier with a single exposure, and move to full-on multi-patterning. In addition, more space can be saved around vias by employing a self-aligned process that eliminates much of the “land” around the via.

As we move beyond 14 nm, technologies like directed self-assembly (DSA) and pattern transfer are being explored as additional ways to create ever finer patterns in a high-volume manufacturing context.

From a device roadmap standpoint, we start with fully-depleted devices, something that IBM continues to support for planar transistors. It’s particularly effective in a silicon-on-insulator (SOI) context, but it also has benefits with bulk silicon.

Of course, the most recognized next step to this is turning that device on its edge into a FinFET or multi-gate transistor. The idea is that you get much better electrostatic control by having a gate at what used to be the top and the bottom – which are now simply two sides because the thing has been flipped on edge. Done exactly that way, it’s a dual-gate device (both sides of the fin); if the top of the fin has a thin oxide cap with the gate over it as well, it’s a tri-gate device.

This is really part of a migration from transistors where the gate controls only one side of the channel (the top of a planar transistor). FinFETs take that to two or three sides; the next obvious step is silicon nano-wires, since now you can surround the channel completely with the gate, controlling all sides in a gate-all-around (GAA) configuration.

Alternative materials to silicon are also under consideration, although nothing we haven’t heard of before. III/V materials look particularly promising for nFETs; germanium or SiGe can fill the bill for pFETs.

Beyond this, we enter the realm of carbon. There’s lots of interest in graphene, but, as a single layer, it has no bandgap, and so it can’t be used for switching: its promise lies more in the RF arena. Rolling graphene up into carbon nanotubes (CNTs) yields the desired bandgap, and that’s the anticipated direction for digital logic.

The other major area of concern is interconnect in general. One somewhat surprising thing that has changed is that reducing dimensions no longer does what it used to do. It used to be that, by shrinking everything, you could stuff more on a wafer and you could get better performance. At the most aggressive technologies, however, that’s no longer the case.

As wires get smaller, the resistance increases, along with the current density. Capacitance between wires grows. Bigger R and bigger C are not helpful in keeping delays under control. IBM is working on lower-? materials to mitigate this.

Meanwhile, there are mechanical concerns with reliability and overall strength: these new materials don’t themselves perform as well mechanically as the older tried-and-true materials. This really gets to be a materials-stack engineering game, with seed layers helping to bond the materials more firmly and to transfer mismatch stresses better. Likewise, capping materials can ensure that the main conducting material stays put and doesn’t migrate into the dielectric that covers it.

Line-to-line leakage is also an issue, largely due to wafer “damage” or imperfections caused by process steps like chemical-mechanical polishing (CMP). IBM in particular is trying to optimize those process steps so that there are fewer opportunities for such leakage.

At some point, all of this becomes too hard to manage, and photonics enters the picture. This literally involves the ability to multiplex multiple signals at different frequencies on a single “conductor,” demuxing them at their destinations and then converting back to electrical signals. All of which requires technology development to be of any use.

So there you have it. The CPA has a roadmap, and this is it. It’s not that they’re doing anything radically different than you might hear from someone else; it’s simply that they want to be sure that everyone understands that they’re in the game just as much as any other foundry you might be able to think of. And if they had a choice as to what you would take away from this article, that would probably be it.

Of course, roadmaps are easy. It’s implementing them that’s a pain in the tuckus…

 

(And the Common Platform Alliance isn’t the only place that 14 nm is being publicly addressed…)

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