feature article
Subscribe Now

Out, Damned Spot!

How to Detect Devices Drawing the Life Blood Out of Your Design

Lurking unseen in CMOS designs, unintended devices may be drawing current. As multiple power domains become common, it’s more likely that unintentional forward-biased diodes are introduced in the design. Forward-biased diodes also can be introduced by circuit design errors or layout design errors in complex circuitry such as digital circuits that contain pass gates and analog circuits.

Forward-biased diodes may draw enough current to cause outright device failure. However, even more worrisome are the ones that don’t draw enough current to cause outright failure, but increase power consumption unnecessarily. These devices need to be detected and addressed so that IC designers can be assured that they are creating high-quality products. A comprehensive verification system will detect these unintended devices that may be drawing the life blood out of your design.

Whether a design is intended for use in power-saving mobile devices or high-performance server applications, power consumption is a critical design limitation. In high-performance devices, heat dissipation limits clock speed—heat dissipated is proportional to power consumed. Every serious PC gamer knows that the clock speed of the processor can be set higher than the manufacturer’s specification if the supply voltage is set a little high and better cooling is applied.

One of the ways power consumption is controlled is by using multiple power domains in a design. Examples of power-saving techniques that rely on multiple power domains include temporarily or permanently reducing the supply voltage to parts of a device or turning off some circuitry.

Here, I illustrate a verification system, using programmable electrical rule checking, to detect forward-biased diodes efficiently [1]. This type of complex problem cannot be dealt with traditional individual point tools. The ability to verify the presence of these unintended devices requires the circuit extraction capability of a traditional LVS tool, the geometric checks of a DRC tool, selective parasitic extraction, and analysis tools.

Diodes that we want versus diodes that we don’t

In this example (Figure 1), there are diodes that are end up being part of the design. For example, there are diodes from the p-substrate to the n+ of the NMOS transistor’s source and drain. There are also diodes from the PMOS transistor’s source and drain to the n-well. These diodes from the NMOS base p+ to the p-substrate and from the PMOS base n+ to the n-well are the ones we are interested in.

Hackney_OutDamnSpot_Figure-1a.jpg

Figure 1: Example of intentional diodes in NMOS and PMOS transistors.

 

To verify these parasitic diodes, we need to address the following.

First, we must ensure that the voltage applied to A is less than or equal to the voltage applied to C (Figure 2).

Hackney_OutDamnSpot_Figure-2.jpg

Figure 2: Voltage check for an intentional diode device.


Second, for the PMOS device, we must ensure that the voltages applied to the source and drain are less than or equal to the voltage applied to the bulk (Figure 3).

Hackney_OutDamnSpot_Figure-3.jpg

Figure 3: Voltage check for PMOS diodes.


Finally, for the NMOS device, we must ensure that the voltages applied to the base is less than or equal to the voltage applied to the source and drain (Figure 4).

Hackney_OutDamnSpot_Figure-4.jpg

Figure 4: Voltage check for NMOS diodes.


Normally the bulk pin of a MOS transistor is tied to the same voltage as the source. So the primary culprits which may be draining power that we don’t intend will be cases where the bulk pin is tied to something else. This is more common than you might expect, especially in multi-voltage domain parts and in analog circuitry. Simply reporting all devices with unusual bulk pin connections isn’t useful because the majority of these will be working as needed in the actual operation of the circuit.

For example, while the bulk pin of mn2 can be at the Vdd level in Figure 5, it isn’t logically possible for this to occur at the same time that mn2’s source pin is connected to ground because both mp1 and mn1 can’t be on at the same time. On the other hand, in figure 6, that same diode can clearly be forward-biased.

Hackney_OutDamnSpot_Figure-5.jpg

Figure 5: Example of circuit layout with mn2 not forward-biased.

 

Hackney_OutDamnSpot_Figure-6.jpg

Figure 6: Example of circuit layout with mn2 forward-biased.


Determining if forward bias can actually occur in real circuits is very hard. Several voltage levels can be propagated to the same device terminal, and determining which scenarios can actually occur is extremely difficult (logic pruning is equivalent to the Boolean ability-to-satisfy problem, which is NP complete).

Figure 7 is an example of forward-biased diodes in an actual circuit.  

Hackney_OutDamnSpot_Figure-7.jpg

Figure 7: Example of actual circuit with forward-biased diodes.           


For the NMOS devices mM8 and mM9, the bulk pin voltages can be less than voltages on d0b and d1b, respectively. For the PMOS devices mM7 and mM10, the bulk pin voltages can be greater than the voltages on d0b and d1b,respectively.

How to spot those troublesome forward-biased diodes

To address the issue of parasitic devices, one can implement a checker that detects forward-biased diodes in reasonable time with minimal “false violations.”

Checks for the forward-biased diodes checks can be performed on schematic data to verify design intent or on layout to verify design implementation. Layout verification tools can use the electrical rule checker’s circuit extraction capability. Devices are recognized in the layout, and a netlist is assembled from the chip’s drawn interconnect.

The idea is to use the tool’s TCL API to implement a verification scheme called “multi-stage filtering.” This strategy applies multiple filters in sequence. Each filter identifies devices that can never be in a forward-biased state. Each filter is more effective at eliminating devices but is also more time-consuming to execute.

To start, you can define the possible voltage levels for each external connection of the design. These voltages are propagated through resistors and transistors to the internal nets to define the worst case potential voltage set for each net.

The first filter simply checks these propagated voltage sets at each device. As an example, if the propagated set of voltages for the net attached to PMOS bulk pin is {2.5 volts and 3 volts} and the drain and source pins both have a propagated voltage set of {0 and 2.5 volts}, the device could never be forward-biased.

However, consider a device that is part of a subcircuit that can be powered down. Then the bulk pin voltage set might be {0 and 2.5 volts}. With source and drain voltages of {0 and 2.5 volts}, it’s possible for the device to fail this simple check.

Subsequent filtering steps consider progressively more complicated logical elimination of impossible states.

A customer used just this approach with Mentor’s Calibre PERC product and achieved a run time of just over two hours on a device with just approximately 49 million devices. The checker reported a few hundred potential violations that the designer then had to verify. The checker found real forward-biased diodes in designs — some of them caused excessive power draw and, in one case, caused a hard part failure. Using this method, the designer was assured that these unintended devices were caught before the IC went into manufacture.

Reference

  1. Grinshpon, A.S. Schubert, Z. Lu, “Using Calibre PERC for Full-Chip Detection of Unintentional Forward-Biased Diodes,” Design Automation Conference 2010.

About the Author

Gregory Hackney manages the PERC, LFD, and LVS engineering groups at Mentor Graphics Corporation. He has more than 30 years of experience in the EDA and semiconductor industries, with responsibilities ranging from managing diverse engineering teams and quality programs to multisite and international program management. Throughout his career, Hackney has held management and executive positions with Applied Micro Circuits Corporation (AMCC), UNISYS Corporation, COMPASS Design Automation, and Silicon Access. Before his current position at Mentor he was Vice President of Engineering for Sycon Design, Inc. He holds a degree in computer science and biology from University of California/San Diego (UCSD).

Leave a Reply

featured blogs
Oct 26, 2020
Do you have a gadget or gizmo that uses sensors in an ingenious or frivolous way? If so, claim your 15 minutes of fame at the virtual Sensors Innovation Fall Week event....
Oct 26, 2020
'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the... [[ Click on the title to access the full blog on the Cadence Community site....
Oct 23, 2020
Processing a component onto a PCB used to be fairly straightforward. Through-hole products, or a single or double row surface mount with a larger centerline rarely offer unique challenges obtaining a proper solder joint. However, as electronics continue to get smaller and con...
Oct 23, 2020
[From the last episode: We noted that some inventions, like in-memory compute, aren'€™t intuitive, being driven instead by the math.] We have one more addition to add to our in-memory compute system. Remember that, when we use a regular memory, what goes in is an address '...

featured video

Demo: Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP

Sponsored by Synopsys

Applications that require sensing on a continuous basis are always on and often battery operated. In this video, the low-power ARC EM9D Processors run a handwriting character recognition neural network graph to infer the letter that is written.

Click here for more information about DesignWare ARC EM9D / EM11D Processors

featured paper

Fundamentals of Precision ADC Noise Analysis

Sponsored by Texas Instruments

Build your knowledge of noise performance with high-resolution delta-sigma ADCs. This e-book covers types of ADC noise, how other components contribute noise to the system, and how these noise sources interact with each other.

Click here to download the whitepaper

Featured Chalk Talk

Addressing Digital Implementation Challenges with Innovative Machine Learning Techniques

Sponsored by Cadence Design Systems

Machine learning is revolutionizing our designs these days with impressive new capabilities. But, have you considered using machine learning to actually create better designs? In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalf of Cadence Design Systems about how Cadence is using machine learning to help us get more out of our design tools - optimizing a wide range of design automation processes go give us better results in less time.

Click here for more information about Innovus Implementation System