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Bandwidth Bravado

Who’s Winning the SerDes Smackdown?

It’s usually a “fair” fight for only a few seconds. 

As soon as one competitor or the other begins to gain any discernible advantage (which generally doesn’t take long), the other one almost immediately ignores the rules and goes for whatever leverage they can get.  Forget the rules; this is war!  Watching the whole thing unfold, an observer is tempted to cry foul…

Which is exactly what the two wrestlers are counting on.  The “villain” jumps from the ring and grabs a folding chair (which was a bit too conveniently left vacant ringside) and proceeds to attack his rival with it.  The crowd roars in disapproval.  The hero dodges the onslaught a couple of times and then takes a direct hit.  The arena resonates with a cacophony of boos.  The hero is down; he’s bleeding.  Then, he begins, ever-so-slowly, to stagger to his feet.

The FPGA Market has always had a lot in common with pro wrestling. 

Marketers “play nice” only as long as the score seems about tied.  At the first sign of a perceived disadvantage, decorum goes out the window in a no-holds-barred cage match to the death.  Press releases fly like folding chairs through the editorial ether, and rhetoric heats up to the boiling point.  If Their FPGA has 170,000 LUTs, Ours MUST have 180,000.  If Their power consumption is milliwatts, Ours must be microwatts.  If Their wider logic cell is worth 1.6 LUT4s, Ours must be worth 1.7. We’ll compare ourselves on any metric we think might make us look good and have a FUD-fest on the ones that don’t.  We’ll stretch every statistic until it almost breaks, and then we’ll swerve to another topic before the casual observer notices any inconsistencies.  We’ll claim victory in contests that no one has ever heard of.

Technology editors LOVE this stuff.

In unrelated news, Xilinx recently demonstrated the 28Gbps SerDes transceivers they will be using in the upcoming Virtex-7 28nm FPGA family.  A few weeks ago, we were treated to a demo of Altera’s pre-release transceivers and saw firsthand a passable eye diagram at a speed of 25 Gbps.  The following week Achronix announced that Intel will be fabricating their upcoming 22nm FPGAs, and those too will have 28 Gbps transceivers.  Now, Xilinx has upped the ante by demonstrating their upcoming transceivers running at 28 Gbps – and what a lovely eye they have.  Remember that none of these transceivers will be in your hands any time soon – Xilinx, Altera and Achronix/Intel are early-on in the traditional new FPGA family cycle of announce, design, hype, fix, sample, leak, release, and ship.  In fact we have probably just passed the “announce” milestone and are heading into the iterative chasm between “design” and “hype”. 

In the spirit of hype, grab a folding chair and we’ll discuss the reason behind all the high-bandwidth hubbub.  It seems that we consumers can never get enough bandwidth.  We want to wirelessly stream 3D 1080p video to our mobile phones, and we really, really don’t want to hear any excuses about limitations or problems related to the fact that we’re in the middle of Death Valley miles from the nearest tower.  With all that need for bandwidth, the companies that buy the biggest, most expensive FPGAs have one simple request: “Please enable us to connect our Bazillion-gigabit optical links to your FPGAs using as few SerDes lanes as possible.”  For next year, a “Bazillion” is 100 Gbps, and that splits up nicely into four lanes of about 25 Gbps each.  When it comes time to release your 28nm or 22nm FPGAs, you’d better have some working 28-gig SerDes transceivers or you’re in deep trouble.

So far in the marketing melee, Altera and Xilinx have each scored a prestige point.  Altera was the first to announce and the first to demonstrate.  We stood in the lab as an engineer brought up a 25 Gpbs link using a test chip looped back to itself.  The eye diagram was open.  Houston, we have SerDes.  The disadvantage of announcing and demonstrating first, however, is that you give your competitor the next shot.  Xilinx then had the luxury of waiting as long as they wanted (but not too long) to give a demonstration more impressive than their rival’s.  It’s easier when the other side has already shown their cards.  Wait, we’re mixing metaphors here.  You just have to pin the other wrestler before the bell.

What did both teams demonstrate that interested us?  Well, to be perfectly honest, we LOVE getting real demos by real engineers.  Real engineering demos give you a sense of the technology that marketing simply cannot match.  All those PowerPoint slides purée-away the essence of engineering and leave you with a certain zero-drama lack of inspiration that is difficult to describe.  That being said, however, SerDes demos are not exactly the most exciting engineering entrees on the menu.  They typically go like this:  “Here you can see the test chip, and we’ve got a frequency counter here, and we’re looping the output back to the input with this cable (for extra points here, we can go through some verifiable length of FR4 to get to the connector, and even sometimes loop through a faux-backplane thingy… and here I’ll reset the scope and then you can see the eye diagram appearing – with a nice big hole that you could drive a (insert favorite metaphor here – how about “folding chair?”) through. 

Yep.  Thar she blows.  Nice big eye.

OK we’re done with the demo, then.  We should point out that both Xilinx and Altera did due diligence to be sure we knew there was nothing up their sleeve, no stored traces on the scope, no trick frequency counters or hinkey probes.  No slipping in MHz for GHz either. That’s right out.  In fact, want to see the demo for yourself?  OK, it’s not live, but feel free to bring a folding chair: http://www.xilinx.com/28gbps

You back?  Hey, wake up!  Next year, we think SerDes II 3D will be in theaters.  Buy your tickets early.

It’s exciting to see that we will actually have these amazingly fast transceivers in our next-generation FPGAs.  Of course, both Xilinx and Altera have a long road ahead to finish fine-tuning transceivers to the production-ready point.  They have to yield out at a high-enough rate to make a profit, they need to work on both ends of the process tolerance scale, and they need to have acceptable jitter and jitter tolerance along with pre-emphasis and equalization to fix things when they don’t go perfectly.  These super-fast transceivers are not the swiss-army variety we have seen in FPGAs of the past and present.  Both companies will have more conventional transceivers to span the range of lower bit-rates and a smaller number of the 28-gig transceivers for just those channels that need the speed.  Optimizing for things like power consumption across such a large range of speeds would be too much of a compromise.  At the same time, just like in pro wrestling, Achronix is sitting at the announcer’s table during the match, grabbing the mic and talking about what’s going to happen when they bring Intel with them into the ring for the final tag-team showdown in 2012…

The family that will house Xilinx’s 28 Gpbs transceivers will be called Virtex-7 HT.  It will be available in three sizes, ranging from 288K LUT4 (equivalent) to 864K LUT4.  The smallest (or, actually, “least enormous”) of these devices will have 4 transceivers at 28Gbps plus 24 “normal” 13Gbps transceivers.  The huge 864K LUT4 device will have 16 of the 28-gig transceivers and 72 13-gig transceivers.  That is a lot more than Altera has thus-far announced for their upcoming Stratix-5 family.  I can hear the folding chair rustling ringside…

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