Rube Goldberg couldn’t have designed a more elegant confluence of convoluted causal relationships. Start analyzing the perplexing paradox of the FPGA synthesis market and each link of the chain reveals a bizarre force vector that eventually doubles back onto itself into an unlikely equilibrium that miraculously has held stable for a full decade despite disruptive forces of epic proportions.
For over a decade now, Synplify has navigated these waters and has continued to survive and thrive through the unlikeliest of conditions. Now in the hands of EDA giant Synopsys, the Synplify family of FPGA synthesis tools continues to evolve – with a major upgrade this fall.
When you put a digital design into an FPGA, there are two technologies that determine whether your design fits or doesn’t fit, whether it meets your timing constraints or does not, whether the power consumption will be within your limits (or those of the FPGA), or whether it fails completely, leaving your project at the mercy of major mulligans. Those two technologies are synthesis and place-and-route.
FPGA companies are painfully aware of this fact. Synthesis and place-and-route are more important than the FPGA fabric architecture, more important than optimally designed hard IP blocks, more important than being first on the latest process node, and more important than choosing the best fab partner. Next to your own design expertise, nothing has a bigger impact on the viability and quality of your FPGA design than the quality of these two software tools.
On the universal scale of software complexity, synthesis and place-and-route both rate a 10 out of 10. You will not develop a commercially viable FPGA synthesis tool in your basement in your spare time. In fact, you will not develop one in your lifetime if you use all your time – and that of a couple of friends. What you’d need is a diverse team of elite specialists, several calendar years of development time, dozens of real-world FPGA designers exercising your software and providing feedback, and hundreds to thousands of real-world designs to help you characterize, correct, and tune your software.
Today, there are four viable FPGA synthesis tools in the world. Synplify from Synopsys (formerly Synplicity), Precision Synthesis from Mentor Graphics, Xilinx Synthesis Technology (XST) from Xilinx, and Quartus Integrated Synthesis (QIS) from Altera. The first two of these are third-party, vendor-independent commercial tools sold by major EDA companies, and the last two are proprietary single-vendor tools distributed by FPGA companies. Let the battle begin.
For the FPGA companies, relying solely on third-party tools for a key technology like synthesis could be a fatal mistake. The difference between bad synthesis and good synthesis is much larger than the difference between the best and worst FPGA. How would you feel about putting the biggest single competitive factor differentiating your product from your rival’s in the hands of a third party? On the other hand, having third-party synthesis support is critical for FPGA vendors because, historically, third-party tools have performed better than the vendors’ own synthesis tools. If the third-party tools supported your competitor and not you, you could be giving up 10%-20% of quality of results across the board.
For the EDA companies, FPGA synthesis represents an entree into the fastest growing segment of semiconductor design – with a defensible technology. It also represents a substantial development and support cost because, as we mentioned, synthesis is one of the most complex software problems on the planet. On the market side, however, selling third-party FPGA synthesis means getting fair value (which is at least a five-digit price tag) with a tool that FPGA vendors give away for free.
How do you compete with free? By offering enough value to persuade people to pay for the difference. As long as the EDA companies can produce synthesis tools that surpass the FPGA vendors’ free tools by a significant margin, they have a chance at a viable business. A better FPGA synthesis tool could save you millions in parts costs, or give your product a significant competitive advantage in performance or power consumption. Paying a few thousand dollars for that is a no-brainer. The minute the EDA vendors’ synthesis offerings fall behind the free tools, however, or even let the free tools get within a reasonable distance, the game is over.
The newest version of the Synplify family of FPGA synthesis tools represents Synopsys’s determination to differentiate their offering from the FPGA vendor-supplied free tools. With the upcoming generation of 28nm FPGAs from Xilinx and Altera, FPGA designs will be growing to almost 2 million logic elements. That means that traditional single-user FPGA design methodologies will have to give way to team-based design. It also means that today’s tools will need big capacity and performance upgrades to handle the humongous designs. Synopsys has responded to this by giving us a reported 4x runtime improvement in certain modes, team-design features to support concurrent engineering, a global placer to improve quality of results, new dynamic power optimization features, and additional support for Synopsys DesignWare IP libraries. The company is also announcing support for new devices, including Altera Stratix V and SiliconBlue’s low-power iCE65.
With the size of the largest FPGA designs headed toward two million logic elements, runtimes for synthesis and place-and-route with full optimization could be as much as several days. With those steps being in the critical iteration loop for debugging and optimizing your FPGA design, long runtimes could bring your design process almost to a halt. Synopsys’s claim of 4x runtime improvement doesn’t come for free. The FAST mode offers a 4x runtime improvement on a single processor, with the additional capability to parallel process on multiple cores working on separate sections of the design. However, your quality of results may be slightly lower than in “normal” mode due to reduced optimization effort. Most design work, however, doesn’t require full optimization. A typical FPGA design will go through dozens of iterations before reaching the final “give it your best shot” full-blown optimization runs. By improving the available performance of all those early and intermediate runs, Synopsys is giving you a major productivity improvement in the main section of the FPGA design process.
Over the past several generations of FPGA technology, timing delays have been increasingly due to interconnect instead of the logic elements themselves. As a result, for synthesis to optimize timing paths correctly, it needs an accurate picture of the layout and the resulting interconnect. For any design where timing optimization is important, physical synthesis – where placement and logic synthesis are performed either as one step, or in a tight iterative loop – is required. For FPGA with third-party synthesis tools, this is difficult because the place-and-route technology is proprietary to the FPGA vendor. For years, EDA companies like Synopsys have offered physical synthesis flows that integrate with FPGA vendor placers in various ways. For this release, Synopsys has added a global placer to Synplify that lets the synthesis tool generate the starting placement itself – with an understanding of the timing requirements of the design. This approach should yield a better result with fewer cycles than the traditional iterative dialogue between synthesis and place-and-route.
There is also a new mode called “Physical Accelerator” that takes an existing design and performs physically-aware optimization. For designs where synthesis and place-and-route are already complete, but some additional optimization is needed, Physical Accelerator gives the option to add some additional boost to the optimization process without the runtime and complexity of a full from-the-beginning physical synthesis flow.
With more FPGAs being designed by teams instead of individuals, the design environment must take team design into account. With this release, Synopsys has added hierarchical project management and concurrent development capabilities to their synthesis offering. Design blocks can be shared internally and re-used without the requirement for floorplanning. Tracking capabilities have been added that allow the review of implementation results and the synthesis options that created them for each hierarchical block of the design. Then those design files and settings can be bundled into a package and transferred to the team leader for integration.
With their previous release, Synopsys began generating switching activity data to enable more robust power estimation. Now, they have added optimizations to the synthesis process that take advantage of that data. The optimizations with this release focus on block memories and DSP blocks – traditional hot spots for dynamic power consumption.
For designers using FPGAs for ASIC prototyping, support for DesignWare libraries is critical. Synopsys has now provided support for all DesignWare building block digital components except for macrocells (like the 8051). By supporting DesignWare blocks directly, there is far less translation and modification necessary to bring up an FPGA prototype of an ASIC design.
This list of improvements is impressive, and it may help to assuage the fears of designers who worry that the Synopsys acquisition of Synplicity meant a slowdown in development and a loss of emphasis in FPGA design tools. The fact remains, however, that EDA suppliers like Synopsys must continue to race fast enough to far outpace the FPGA vendors’ own internal synthesis development teams, lest they suddenly become irrelevant. For the moment, at least, the EDA industry’s flagship FPGA-specific tool technology is still alive and well.